Jason T. SU

Person

Los Altos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for timing closure
- Patent number 9,223,920
- Issue date Dec 29, 2015
- Marvell World Trade Ltd.
- Jason T. Su
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit memory device with read-disturb control
- Patent number 9,142,286
- Issue date Sep 22, 2015
- Applied Micro Circuits Corporation
- Jason T Su
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable resistance-modulated write assist for a memory device
- Patent number 8,964,452
- Issue date Feb 24, 2015
- Applied Micro Circuits Corporation
- Jason T. Su
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for timing closure
- Patent number 8,689,162
- Issue date Apr 1, 2014
- Marvell World Trade Ltd.
- Jason T. Su
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for supplying power to a static random access...
- Patent number 8,582,387
- Issue date Nov 12, 2013
- Marvell International Ltd.
- Jason T Su
- G11 - INFORMATION STORAGE
Information Patent Grant
Processor with memory delayed bit line precharging
- Patent number 8,526,257
- Issue date Sep 3, 2013
- Marvell World Trade Ltd.
- Sehat Sutardja
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge-injection sense-amp logic
- Patent number 8,451,041
- Issue date May 28, 2013
- Marvell World Trade Ltd.
- Jason T. Su
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Write-assist and power-down circuit for low power SRAM applications
- Patent number 8,310,894
- Issue date Nov 13, 2012
- Marvell International Ltd.
- Jason T. Su
- G11 - INFORMATION STORAGE
Information Patent Grant
Processor instruction cache with dual-read modes
- Patent number 8,295,110
- Issue date Oct 23, 2012
- Marvell World Trade Ltd.
- Sehat Sutardja
- G11 - INFORMATION STORAGE
Information Patent Grant
Aysmmetric sense-amp flip-flop
- Patent number 8,164,363
- Issue date Apr 24, 2012
- Marvell International Ltd.
- Jason Su
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Address decoder
- Patent number 8,164,972
- Issue date Apr 24, 2012
- Marvell International Ltd.
- Jason T. Su
- G11 - INFORMATION STORAGE
Information Patent Grant
Processor instruction cache with dual-read modes
- Patent number 8,089,823
- Issue date Jan 3, 2012
- Marvell World Trade Ltd.
- Sehat Sutardja
- G11 - INFORMATION STORAGE
Information Patent Grant
Processor instruction cache with dual-read modes
- Patent number 8,027,218
- Issue date Sep 27, 2011
- Marvell World Trade Ltd.
- Sehat Sutardja
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock gater system
- Patent number 7,990,199
- Issue date Aug 2, 2011
- Marvell International Ltd.
- Jason T. Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High boosting-ratio/low-switching-delay level shifter
- Patent number 7,965,123
- Issue date Jun 21, 2011
- Marvell International Ltd.
- Jason Su
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Asymmetric sense-amp flip-flop
- Patent number 7,855,587
- Issue date Dec 21, 2010
- Marvell International Ltd.
- Jason Su
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Address decoder
- Patent number 7,848,173
- Issue date Dec 7, 2010
- Marvell International Ltd.
- Jason T. Su
- G11 - INFORMATION STORAGE
Information Patent Grant
Write-assist and power-down circuit for low power SRAM applications
- Patent number 7,835,217
- Issue date Nov 16, 2010
- Marvell International Ltd.
- Jason T. Su
- G11 - INFORMATION STORAGE
Information Patent Grant
Processor instruction cache with dual-read modes
- Patent number 7,787,324
- Issue date Aug 31, 2010
- Marvell World Trade Ltd.
- Sehat Sutardja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High boosting-ratio/low-switching-delay level shifter
- Patent number 7,777,550
- Issue date Aug 17, 2010
- Marvell International Ltd.
- Jason Su
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock gater system
- Patent number 7,639,057
- Issue date Dec 29, 2009
- Marvell International Ltd.
- Jason T. Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write-assist and power-down circuit for low power SRAM applications
- Patent number 7,596,012
- Issue date Sep 29, 2009
- Marvell International Ltd.
- Jason T. Su
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT MEMORY DEVICE WITH READ-DISTURB CONTROL
- Publication number 20140307500
- Publication date Oct 16, 2014
- Applied Micro Circuits Corporation
- Jason T SU
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR TIMING CLOSURE
- Publication number 20140218093
- Publication date Aug 7, 2014
- Marvell World Trade Ltd.
- Jason T. SU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE RESISTANCE-MODULATED WRITE ASSIST FOR A MEMORY DEVICE
- Publication number 20140177356
- Publication date Jun 26, 2014
- Applied Micro Circuits Corporation
- Jason T. Su
- G11 - INFORMATION STORAGE
Information Patent Application
PROCESSOR WITH MEMORY DELAYED BIT LINE PRECHARGING
- Publication number 20130044555
- Publication date Feb 21, 2013
- Marvell World Trade Ltd.
- Sehat Sutardja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR TIMING CLOSURE
- Publication number 20120068754
- Publication date Mar 22, 2012
- Jason T. SU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES
- Publication number 20120014196
- Publication date Jan 19, 2012
- Sehat Sutardja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Charge-Injection Sense-Amp Logic
- Publication number 20120013379
- Publication date Jan 19, 2012
- Jason T. Su
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES
- Publication number 20100329058
- Publication date Dec 30, 2010
- Sehat Sutardja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High Boosting-Ratio/Low-Switching-Delay Level Shifter
- Publication number 20100271105
- Publication date Oct 28, 2010
- Jason Su
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES
- Publication number 20080189518
- Publication date Aug 7, 2008
- Sehat Sutardja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor Instruction Cache with Dual-Read Modes
- Publication number 20080165602
- Publication date Jul 10, 2008
- Sehat Sutardja
- G06 - COMPUTING CALCULATING COUNTING

Jason T. SU

Person

Patents Grantslast 30 patents

Method and apparatus for timing closure

Integrated circuit memory device with read-disturb control

Programmable resistance-modulated write assist for a memory device

Method and apparatus for timing closure

Method and apparatus for supplying power to a static random access...

Processor with memory delayed bit line precharging

Charge-injection sense-amp logic

Write-assist and power-down circuit for low power SRAM applications

Processor instruction cache with dual-read modes

Aysmmetric sense-amp flip-flop

Address decoder

Processor instruction cache with dual-read modes

Processor instruction cache with dual-read modes

Clock gater system

High boosting-ratio/low-switching-delay level shifter

Asymmetric sense-amp flip-flop

Address decoder

Write-assist and power-down circuit for low power SRAM applications

Processor instruction cache with dual-read modes

High boosting-ratio/low-switching-delay level shifter

Clock gater system

Write-assist and power-down circuit for low power SRAM applications

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT MEMORY DEVICE WITH READ-DISTURB CONTROL

METHOD AND APPARATUS FOR TIMING CLOSURE

PROGRAMMABLE RESISTANCE-MODULATED WRITE ASSIST FOR A MEMORY DEVICE

PROCESSOR WITH MEMORY DELAYED BIT LINE PRECHARGING

METHOD AND APPARATUS FOR TIMING CLOSURE

PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES

Charge-Injection Sense-Amp Logic

PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES

High Boosting-Ratio/Low-Switching-Delay Level Shifter

PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES

Processor Instruction Cache with Dual-Read Modes