Jaspreet S. Gandhi

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Thermal pads between stacked semiconductor dies and associated syst...
- Patent number 12,033,980
- Issue date Jul 9, 2024
- Micron Technology, Inc.
- Jaspreet S. Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fanout integration for stacked silicon package assembly
- Patent number 12,027,493
- Issue date Jul 2, 2024
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Universal interposer for a semiconductor package
- Patent number 11,901,300
- Issue date Feb 13, 2024
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of manufacturing stacked semiconductor die assemblies with...
- Patent number 11,776,877
- Issue date Oct 3, 2023
- Micron Technology, Inc.
- Sameer S. Vadhavkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device assembly with through-mold cooling channel for...
- Patent number 11,688,664
- Issue date Jun 27, 2023
- Micron Technology, Inc.
- Bradley R. Bitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked semiconductor die assemblies with multiple thermal paths an...
- Patent number 11,594,462
- Issue date Feb 28, 2023
- Micron Technology, Inc.
- Steven K. Groothuis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked silicon package assembly having vertical thermal management
- Patent number 11,488,936
- Issue date Nov 1, 2022
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package integration for laterally mounted IC dies with dissimilar s...
- Patent number 11,373,989
- Issue date Jun 28, 2022
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked silicon package assembly having thermal management
- Patent number 11,355,412
- Issue date Jun 7, 2022
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package assembly with enhanced solder resist crack resistance
- Patent number 11,315,858
- Issue date Apr 26, 2022
- Xilinx, Inc.
- Yu Hsiang Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Modular stacked silicon package assembly
- Patent number 11,302,674
- Issue date Apr 12, 2022
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package assembly with stress decoupled interconnect layer
- Patent number 11,282,775
- Issue date Mar 22, 2022
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density routing for heterogeneous package integration
- Patent number 11,282,776
- Issue date Mar 22, 2022
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package assembly with enhanced interconnects and method for fa...
- Patent number 11,217,550
- Issue date Jan 4, 2022
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked silicon package assembly having thermal management using ph...
- Patent number 11,195,780
- Issue date Dec 7, 2021
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked silicon package assembly having thermal management
- Patent number 11,145,566
- Issue date Oct 12, 2021
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonding pads with thermal pathways
- Patent number 11,139,258
- Issue date Oct 5, 2021
- Micron Technology, Inc.
- Jaspreet S Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structures for validating package fabrication process
- Patent number 11,127,643
- Issue date Sep 21, 2021
- Xilinx, Inc.
- Vadim Heyfitch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die device structures and methods
- Patent number 11,114,360
- Issue date Sep 7, 2021
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package integration for high bandwidth memory
- Patent number 10,971,474
- Issue date Apr 6, 2021
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder joints for board level reliability
- Patent number 10,930,611
- Issue date Feb 23, 2021
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a semiconductor device assembly with throu...
- Patent number 10,916,487
- Issue date Feb 9, 2021
- Micron Technology, Inc.
- Bradley R. Bitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices having conductive vias and methods of forming...
- Patent number 10,886,196
- Issue date Jan 5, 2021
- Micron Technology, Inc.
- Jaspreet S. Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density substrate and stacked silicon package assembly having...
- Patent number 10,879,157
- Issue date Dec 29, 2020
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Interconnect structures with intermetallic palladium joints and ass...
- Patent number 10,861,825
- Issue date Dec 8, 2020
- Micron Technology, Inc.
- Jaspreet S. Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder bond site including an opening with discontinuous profile
- Patent number 10,847,382
- Issue date Nov 24, 2020
- Micron Technology, Inc.
- Jaspreet S. Gandhi
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Package integration for memory devices
- Patent number 10,770,430
- Issue date Sep 8, 2020
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device assembly with heat transfer structure formed f...
- Patent number 10,748,878
- Issue date Aug 18, 2020
- Micron Technology, Inc.
- Sameer S. Vadhavkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming interconnect assemblies with probed bond pads
- Patent number 10,741,460
- Issue date Aug 11, 2020
- Micron Technology, Inc.
- Owen R. Fay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked semiconductor die assemblies with multiple thermal paths an...
- Patent number 10,741,468
- Issue date Aug 11, 2020
- Micron Technology, Inc.
- Steven K. Groothuis
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYST...
- Publication number 20240347511
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Jaspreet S. Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED TIME-OF-FLIGHT MODULE
- Publication number 20240241231
- Publication date Jul 18, 2024
- Meta Platforms Technologies, LLC
- Jack Diepen Mumbo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE INTEGRATION WITH HYBRID BONDED BRIDGE DIE
- Publication number 20240203968
- Publication date Jun 20, 2024
- Xilinx, Inc.
- Jaspreet Singh GANDHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH...
- Publication number 20230395463
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Sameer S. Vadhavkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNIVERSAL INTERPOSER FOR A SEMICONDUCTOR PACKAGE
- Publication number 20230268280
- Publication date Aug 24, 2023
- Xilinx, Inc.
- Jaspreet Singh GANDHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH...
- Publication number 20220013434
- Publication date Jan 13, 2022
- Micron Technology, Inc.
- Sameer S. Vadhavkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MODULAR STACKED SILICON PACKAGE ASSEMBLY
- Publication number 20210366873
- Publication date Nov 25, 2021
- Xilinx, Inc.
- Jaspreet Singh GANDHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SILICON PACKAGE ASSEMBLY HAVING THERMAL MANAGEMENT
- Publication number 20210249328
- Publication date Aug 12, 2021
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SILICON PACKAGE ASSEMBLY HAVING VERTICAL THERMAL MANAGEMENT
- Publication number 20210193620
- Publication date Jun 24, 2021
- Xilinx, Inc.
- Gamal Refai-Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FANOUT INTEGRATION FOR STACKED SILICON PACKAGE ASSEMBLY
- Publication number 20210134757
- Publication date May 6, 2021
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE ASSEMBLY WITH THROU...
- Publication number 20210125899
- Publication date Apr 29, 2021
- Micron Technology, Inc.
- Bradley R. Bitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYST...
- Publication number 20200411482
- Publication date Dec 31, 2020
- Micron Technology, Inc.
- Jaspreet S. Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH MULTIPLE THERMAL PATHS AN...
- Publication number 20200350224
- Publication date Nov 5, 2020
- Micron Technology, Inc.
- Steven K. Groothuis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE INTEGRATION FOR MEMORY DEVICES
- Publication number 20200303341
- Publication date Sep 24, 2020
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BONDING PADS WITH THERMAL PATHWAYS
- Publication number 20200176404
- Publication date Jun 4, 2020
- Micron Technology, Inc.
- JASPREET S. GANDHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY SUBSTRATE AND STACKED SILICON PACKAGE ASSEMBLY HAVING...
- Publication number 20200161229
- Publication date May 21, 2020
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
STACKED SILICON PACKAGE ASSEMBLY HAVING THERMAL MANAGEMENT
- Publication number 20200105642
- Publication date Apr 2, 2020
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE ASSEMBLY WITH ENHANCED INTERCONNECTS AND METHOD FOR FA...
- Publication number 20200035635
- Publication date Jan 30, 2020
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLDER BOND SITE INCLUDING AN OPENING WITH DISCONTINUOUS PROFILE
- Publication number 20190393050
- Publication date Dec 26, 2019
- Micron Technology, Inc.
- Jaspreet S. Gandhi
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
SEMICONDUCTOR DEVICE ASSEMBLY WITH HEAT TRANSFER STRUCTURE FORMED F...
- Publication number 20190348401
- Publication date Nov 14, 2019
- Micron Technology, Inc.
- Sameer S. Vadhavkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE ASSEMBLY WITH THROUGH-MOLD COOLING CHANNEL FOR...
- Publication number 20190333840
- Publication date Oct 31, 2019
- Micron Technology, Inc.
- Bradley R. Bitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNIFORM BACK SIDE EXPOSURE OF THROUGH-SILICON VIAS
- Publication number 20190304799
- Publication date Oct 3, 2019
- Micron Technology, Inc.
- Jaspreet S. Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY ROUTING FOR HETEROGENEOUS PACKAGE INTEGRATION
- Publication number 20190259695
- Publication date Aug 22, 2019
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- G01 - MEASURING TESTING
Information Patent Application
INTERCONNECT STRUCTURES WITH INTERMETALLIC PALLADIUM JOINTS AND ASS...
- Publication number 20190237434
- Publication date Aug 1, 2019
- Micron Technology, Inc.
- Jaspreet S. Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE ASSEMBLY WITH HEAT TRANSFER STRUCTURE FORMED F...
- Publication number 20190229096
- Publication date Jul 25, 2019
- Micron Technology, Inc.
- Sameer S. Vadhavkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES HAVING CONDUCTIVE VIAS AND METHODS OF FORMING...
- Publication number 20190229039
- Publication date Jul 25, 2019
- Micron Technology, Inc.
- Jaspreet S. Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE ASSEMBLY WITH ENHANCED INTERCONNECTS AND METHOD FOR FA...
- Publication number 20190131265
- Publication date May 2, 2019
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH MULTIPLE THERMAL PATHS AN...
- Publication number 20190122950
- Publication date Apr 25, 2019
- Micron Technology, Inc.
- Steven K. Groothuis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE TEST APPARATUSES
- Publication number 20190072608
- Publication date Mar 7, 2019
- Micron Technology, Inc.
- Jaspreet S. Gandhi
- G01 - MEASURING TESTING
Information Patent Application
SOLDER BOND SITE INCLUDING AN OPENING WITH DISCONTINUOUS PROFILE
- Publication number 20190074194
- Publication date Mar 7, 2019
- Micron Technology, Inc.
- Jaspreet S. Gandhi
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Jaspreet S. Gandhi

Person

Patents Grantslast 30 patents

Thermal pads between stacked semiconductor dies and associated syst...

Fanout integration for stacked silicon package assembly

Universal interposer for a semiconductor package

Methods of manufacturing stacked semiconductor die assemblies with...

Semiconductor device assembly with through-mold cooling channel for...

Stacked semiconductor die assemblies with multiple thermal paths an...

Stacked silicon package assembly having vertical thermal management

Package integration for laterally mounted IC dies with dissimilar s...

Stacked silicon package assembly having thermal management

Chip package assembly with enhanced solder resist crack resistance

Modular stacked silicon package assembly

Chip package assembly with stress decoupled interconnect layer

High density routing for heterogeneous package integration

Chip package assembly with enhanced interconnects and method for fa...

Stacked silicon package assembly having thermal management using ph...

Stacked silicon package assembly having thermal management

Bonding pads with thermal pathways

Test structures for validating package fabrication process

Multi-die device structures and methods

Package integration for high bandwidth memory

Solder joints for board level reliability

Method for manufacturing a semiconductor device assembly with throu...

Semiconductor devices having conductive vias and methods of forming...

High density substrate and stacked silicon package assembly having...

Interconnect structures with intermetallic palladium joints and ass...

Solder bond site including an opening with discontinuous profile

Package integration for memory devices

Semiconductor device assembly with heat transfer structure formed f...

Methods for forming interconnect assemblies with probed bond pads

Stacked semiconductor die assemblies with multiple thermal paths an...

Patents Applicationslast 30 patents

THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYST...

STACKED TIME-OF-FLIGHT MODULE

CHIP PACKAGE INTEGRATION WITH HYBRID BONDED BRIDGE DIE

METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH...

UNIVERSAL INTERPOSER FOR A SEMICONDUCTOR PACKAGE

METHODS OF MANUFACTURING STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH...

MODULAR STACKED SILICON PACKAGE ASSEMBLY

STACKED SILICON PACKAGE ASSEMBLY HAVING THERMAL MANAGEMENT

STACKED SILICON PACKAGE ASSEMBLY HAVING VERTICAL THERMAL MANAGEMENT

FANOUT INTEGRATION FOR STACKED SILICON PACKAGE ASSEMBLY

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE ASSEMBLY WITH THROU...

THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYST...

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH MULTIPLE THERMAL PATHS AN...

PACKAGE INTEGRATION FOR MEMORY DEVICES

BONDING PADS WITH THERMAL PATHWAYS

HIGH DENSITY SUBSTRATE AND STACKED SILICON PACKAGE ASSEMBLY HAVING...

STACKED SILICON PACKAGE ASSEMBLY HAVING THERMAL MANAGEMENT

CHIP PACKAGE ASSEMBLY WITH ENHANCED INTERCONNECTS AND METHOD FOR FA...

SOLDER BOND SITE INCLUDING AN OPENING WITH DISCONTINUOUS PROFILE

SEMICONDUCTOR DEVICE ASSEMBLY WITH HEAT TRANSFER STRUCTURE FORMED F...

SEMICONDUCTOR DEVICE ASSEMBLY WITH THROUGH-MOLD COOLING CHANNEL FOR...

UNIFORM BACK SIDE EXPOSURE OF THROUGH-SILICON VIAS

HIGH DENSITY ROUTING FOR HETEROGENEOUS PACKAGE INTEGRATION

INTERCONNECT STRUCTURES WITH INTERMETALLIC PALLADIUM JOINTS AND ASS...

SEMICONDUCTOR DEVICE ASSEMBLY WITH HEAT TRANSFER STRUCTURE FORMED F...

SEMICONDUCTOR DEVICES HAVING CONDUCTIVE VIAS AND METHODS OF FORMING...

CHIP PACKAGE ASSEMBLY WITH ENHANCED INTERCONNECTS AND METHOD FOR FA...

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH MULTIPLE THERMAL PATHS AN...

SEMICONDUCTOR DEVICE TEST APPARATUSES

SOLDER BOND SITE INCLUDING AN OPENING WITH DISCONTINUOUS PROFILE