Javed S. Barkatullah

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus for power consumption reduction
- Patent number 7,562,316
- Issue date Jul 14, 2009
- Intel Corporation
- James W. Tschanz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PLL with controlled VCO bias
- Patent number 7,342,426
- Issue date Mar 11, 2008
- Intel Corporation
- Nasser A. Kurd
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Frequency management apparatus, systems, and methods
- Patent number 7,282,966
- Issue date Oct 16, 2007
- Intel Corporation
- Siva G. Narendra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for detecting on-die voltage variations
- Patent number 7,133,751
- Issue date Nov 7, 2006
- Intel Corporation
- Nasser A. Kurd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit to manage and lower clock inaccuracies of integrated circuits
- Patent number 7,102,402
- Issue date Sep 5, 2006
- Intel Corporation
- Nasser A. Kurd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for power consumption reduction
- Patent number 7,096,433
- Issue date Aug 22, 2006
- Intel Corporation
- James W. Tschanz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive frequency clock generation system
- Patent number 7,042,259
- Issue date May 9, 2006
- Intel Corporation
- Nasser A. Kurd
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive body bias for clock skew compensation
- Patent number 7,015,741
- Issue date Mar 21, 2006
- Intel Corporation
- James W. Tschanz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Smart buffer circuit to match a delay over a range of loads
- Patent number 7,009,437
- Issue date Mar 7, 2006
- Intel Corporation
- Thomas D. Fletcher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for optimizing clock distribution to reduce th...
- Patent number 6,934,872
- Issue date Aug 23, 2005
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive frequency clock signal
- Patent number 6,922,111
- Issue date Jul 26, 2005
- Intel Corporation
- Nasser A. Kurd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock signal generation and distribution via ring oscillators
- Patent number 6,922,112
- Issue date Jul 26, 2005
- Intel Corporation
- Nasser A. Kurd
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for detecting on-die voltage variations
- Patent number 6,882,238
- Issue date Apr 19, 2005
- Intel Corporation
- Nasser A. Kurd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for correcting a clock duty cycle in a clock d...
- Patent number 6,750,689
- Issue date Jun 15, 2004
- Intel Corporation
- Thomas D. Fletcher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Automated clock alignment for testing processors in a bypass mode
- Patent number 6,704,892
- Issue date Mar 9, 2004
- Intel Corporation
- Nasser A. Kurd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating a 2-phase clock using a non-50% divider circuit
- Patent number 6,629,255
- Issue date Sep 30, 2003
- Intel Corporation
- Javed S. Barkatullah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital clock skew detection and phase alignment
- Patent number 6,622,255
- Issue date Sep 16, 2003
- Intel Corporation
- Nasser A. Kurd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock distribution system for selectively enabling clock signals to...
- Patent number 6,611,920
- Issue date Aug 26, 2003
- Intel Corporation
- Thomas D. Fletcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core clock correction in a 2/n mode clocking scheme
- Patent number 6,268,749
- Issue date Jul 31, 2001
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core clock correction in a 2/N mode clocking scheme
- Patent number 6,208,180
- Issue date Mar 27, 2001
- Intel Corporation
- Matthew A. Fisch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for clock skew compensation
- Patent number 6,192,092
- Issue date Feb 20, 2001
- Intel Corp.
- Rommel O. Dizon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating 2/N mode bus clock signals
- Patent number 6,104,219
- Issue date Aug 15, 2000
- Intel Corporation
- Javed S. Barkatullah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core clock correction in a 2/N mode clocking scheme
- Patent number 5,834,956
- Issue date Nov 10, 1998
- Intel Corporation
- Chakrapani Pathikonda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating 2/N mode bus clock signals
- Patent number 5,821,784
- Issue date Oct 13, 1998
- Intel Corporation
- Javed S. Barkatullah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for synchronizing clock signals in a multiple...
- Patent number 5,706,485
- Issue date Jan 6, 1998
- Intel Corporation
- Javed Barkatullah
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR CONVERTING 2D-IMAGES AND VIDEOS TO 3D FOR...
- Publication number 20150116457
- Publication date Apr 30, 2015
- Barkatech Consulting, LLC
- JAVED SABIR BARKATULLAH
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS FOR GENERATING ENHANCED 3D-EFFECTS FOR REAL-TI...
- Publication number 20150116458
- Publication date Apr 30, 2015
- Barkatech Consulting, LLC
- JAVED SABIR BARKATULLAH
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Clock modulation circuits with time averaging
- Publication number 20070238434
- Publication date Oct 11, 2007
- Nasser Kurd
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PLL with controlled VCO bias
- Publication number 20070046343
- Publication date Mar 1, 2007
- Nasser A. Kurd
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for power consumption reduction
- Publication number 20060259890
- Publication date Nov 16, 2006
- Intel Corporation
- James W. Tschanz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Frequency management apparatus, systems, and methods
- Publication number 20060066376
- Publication date Mar 30, 2006
- Siva G. Narendra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive frequency clock generation system
- Publication number 20050218955
- Publication date Oct 6, 2005
- Intel Corporation
- Nasser A. Kurd
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for detecting on-die voltage variations
- Publication number 20050184764
- Publication date Aug 25, 2005
- Nasser A. Kurd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive body bias for clock skew compensation
- Publication number 20050134361
- Publication date Jun 23, 2005
- Intel Corporation
- James W. Tschanz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for power consumption reduction
- Publication number 20050102642
- Publication date May 12, 2005
- Intel Corporation
- James W. Tschanz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Smart buffer circuit to match a delay over a range of loads
- Publication number 20040217792
- Publication date Nov 4, 2004
- Thomas D. Fletcher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for detecting on-die voltage variations
- Publication number 20040183613
- Publication date Sep 23, 2004
- Nasser A. Kurd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive frequency clock signal
- Publication number 20040119521
- Publication date Jun 24, 2004
- Nasser A. Kurd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock signal generation and distribution via ring oscillators
- Publication number 20030234694
- Publication date Dec 25, 2003
- Nasser A. Kurd
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuit to manage and lower clock inaccuracies of integrated circuits
- Publication number 20030221143
- Publication date Nov 27, 2003
- Nasser A. Kurd
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for optimizing clock distribution to reduce th...
- Publication number 20030115493
- Publication date Jun 19, 2003
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for correcting a clock duty cycle
- Publication number 20020140478
- Publication date Oct 3, 2002
- Thomas D. Fletcher
- H03 - BASIC ELECTRONIC CIRCUITRY

Javed S. Barkatullah

Person

Patents Grantslast 30 patents

Apparatus for power consumption reduction

PLL with controlled VCO bias

Frequency management apparatus, systems, and methods

Method and apparatus for detecting on-die voltage variations

Circuit to manage and lower clock inaccuracies of integrated circuits

Method for power consumption reduction

Adaptive frequency clock generation system

Adaptive body bias for clock skew compensation

Smart buffer circuit to match a delay over a range of loads

Method and apparatus for optimizing clock distribution to reduce th...

Adaptive frequency clock signal

Clock signal generation and distribution via ring oscillators

Method and apparatus for detecting on-die voltage variations

Method and apparatus for correcting a clock duty cycle in a clock d...

Automated clock alignment for testing processors in a bypass mode

Generating a 2-phase clock using a non-50% divider circuit

Digital clock skew detection and phase alignment

Clock distribution system for selectively enabling clock signals to...

Core clock correction in a 2/n mode clocking scheme

Core clock correction in a 2/N mode clocking scheme

Method and apparatus for clock skew compensation

Method and apparatus for generating 2/N mode bus clock signals

Core clock correction in a 2/N mode clocking scheme

Method and apparatus for generating 2/N mode bus clock signals

Method and apparatus for synchronizing clock signals in a multiple...

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR CONVERTING 2D-IMAGES AND VIDEOS TO 3D FOR...

METHOD AND APPARATUS FOR GENERATING ENHANCED 3D-EFFECTS FOR REAL-TI...

Clock modulation circuits with time averaging

PLL with controlled VCO bias

Method and apparatus for power consumption reduction

Frequency management apparatus, systems, and methods

Adaptive frequency clock generation system

Method and apparatus for detecting on-die voltage variations

Adaptive body bias for clock skew compensation

Method and apparatus for power consumption reduction

Smart buffer circuit to match a delay over a range of loads

Method and apparatus for detecting on-die voltage variations

Adaptive frequency clock signal

Clock signal generation and distribution via ring oscillators

Circuit to manage and lower clock inaccuracies of integrated circuits

Method and apparatus for optimizing clock distribution to reduce th...

Method and apparatus for correcting a clock duty cycle