JAVID JAFFARI

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Binary neural network accelerator engine methods and systems
- Patent number 11,488,002
- Issue date Nov 1, 2022
- ATLAZO, INC.
- Javid Jaffari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for sparse neural network acceleration
- Patent number 10,871,964
- Issue date Dec 22, 2020
- QUALCOMM Incorporated
- Yatish Girish Turakhia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compact arithmetic accelerator for data processing devices, systems...
- Patent number 10,713,045
- Issue date Jul 14, 2020
- ATLAZO, INC.
- Javid Jaffari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supply voltage droop management circuits for reducing or avoiding s...
- Patent number 10,296,076
- Issue date May 21, 2019
- QUALCOMM Incorporated
- Javid Jaffari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power gate placement techniques in three-dimensional (3D) integrate...
- Patent number 9,754,923
- Issue date Sep 5, 2017
- QUALCOMM Incorporated
- Jing Xie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for a hybrid parallel-serial memory access
- Patent number 9,747,038
- Issue date Aug 29, 2017
- QUALCOMM Incorporated
- Javid Jaffari
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DSP BASED COMPUTE ENGINE FOR EXECUTING MATRIX OPERATIONS
- Publication number 20240220574
- Publication date Jul 4, 2024
- Meta Platforms Technologies, LLC
- Shiyu Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PARALLELISM
- Publication number 20240220255
- Publication date Jul 4, 2024
- Meta Platforms Technologies, LLC
- Reza Tusi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAPPING HARDWARE COMPONENTS TO A SERIES OF CALCULATIONS
- Publication number 20240220281
- Publication date Jul 4, 2024
- Meta Platforms Technologies, LLC
- Vignesh Vivekraja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ARCHITECTURE AND AN INSTRUCTION SET ARCHITECTURE FOR MACHI...
- Publication number 20240220273
- Publication date Jul 4, 2024
- Meta Platforms Technologies, LLC
- Vignesh Vivekraja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POLYMORPHIC TWO-DIMENSIONAL REGISTER FILE
- Publication number 20240220256
- Publication date Jul 4, 2024
- Meta Platforms Technologies, LLC
- Reza Tusi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA COMPRESSION USING INSTRUCTION SET ARCHITECTURE
- Publication number 20240220259
- Publication date Jul 4, 2024
- Meta Platforms Technologies, LLC
- Tomonari Tohara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEQUENCE OF OPERATIONS IN AN SIMD VLIW PROCESSOR FOR MACHINE-LEARNI...
- Publication number 20240220779
- Publication date Jul 4, 2024
- Meta Platforms Technologies, LLC
- Vignesh Vivekraja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR PEAK POWER CONTROL
- Publication number 20230168729
- Publication date Jun 1, 2023
- Facebook Technologies, LLC
- Vlad Fruchter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BINARY NEURAL NETWORK ACCELERATOR ENGINE METHODS AND SYSTEMS
- Publication number 20190251425
- Publication date Aug 15, 2019
- Atlazo, Inc.
- Javid Jaffari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPACT ARITHMETIC ACCELERATOR FOR DATA PROCESSING DEVICES, SYSTEMS...
- Publication number 20190235867
- Publication date Aug 1, 2019
- Atlazo, Inc.
- Javid Jaffari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR SPARSE NEURAL NETWORK ACCELERATION
- Publication number 20180189056
- Publication date Jul 5, 2018
- QUALCOMM Incorporated
- Yatish Girish TURAKHIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-POWER ARCHITECTURE FOR SPARSE NEURAL NETWORK
- Publication number 20180164866
- Publication date Jun 14, 2018
- QUALCOMM Incorporated
- Yatish Girish TURAKHIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPLY VOLTAGE DROOP MANAGEMENT CIRCUITS FOR REDUCING OR AVOIDING S...
- Publication number 20170329391
- Publication date Nov 16, 2017
- QUALCOMM Incorporated
- Javid Jaffari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-RANK COLLISION REDUCTION IN A HYBRID PARALLEL-SERIAL MEMORY S...
- Publication number 20170262367
- Publication date Sep 14, 2017
- QUALCOMM Incorporated
- DEXTER TAMIO CHUN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR A HYBRID PARALLEL-SERIAL MEMORY ACCESS
- Publication number 20170160928
- Publication date Jun 8, 2017
- QUALCOMM Incorporated
- JAVID JAFFARI
- G06 - COMPUTING CALCULATING COUNTING

JAVID JAFFARI

Person

Patents Grantslast 30 patents

Binary neural network accelerator engine methods and systems

Architecture for sparse neural network acceleration

Compact arithmetic accelerator for data processing devices, systems...

Supply voltage droop management circuits for reducing or avoiding s...

Power gate placement techniques in three-dimensional (3D) integrate...

Systems and methods for a hybrid parallel-serial memory access

Patents Applicationslast 30 patents

DSP BASED COMPUTE ENGINE FOR EXECUTING MATRIX OPERATIONS

DATA PARALLELISM

MAPPING HARDWARE COMPONENTS TO A SERIES OF CALCULATIONS

HARDWARE ARCHITECTURE AND AN INSTRUCTION SET ARCHITECTURE FOR MACHI...

POLYMORPHIC TWO-DIMENSIONAL REGISTER FILE

DATA COMPRESSION USING INSTRUCTION SET ARCHITECTURE

SEQUENCE OF OPERATIONS IN AN SIMD VLIW PROCESSOR FOR MACHINE-LEARNI...

SYSTEMS AND METHODS FOR PEAK POWER CONTROL

BINARY NEURAL NETWORK ACCELERATOR ENGINE METHODS AND SYSTEMS

COMPACT ARITHMETIC ACCELERATOR FOR DATA PROCESSING DEVICES, SYSTEMS...

ARCHITECTURE FOR SPARSE NEURAL NETWORK ACCELERATION

LOW-POWER ARCHITECTURE FOR SPARSE NEURAL NETWORK

SUPPLY VOLTAGE DROOP MANAGEMENT CIRCUITS FOR REDUCING OR AVOIDING S...

MULTI-RANK COLLISION REDUCTION IN A HYBRID PARALLEL-SERIAL MEMORY S...

SYSTEMS AND METHODS FOR A HYBRID PARALLEL-SERIAL MEMORY ACCESS