Javier DeLaCruz

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Summit, NJ, US

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Patents Grantslast 30 patents

Information Patent Grant
Elongated pad structure
- Patent number 10,050,003
- Issue date Aug 14, 2018
- eSilicon Corporation
- Javier DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wireless probes
- Patent number 10,018,670
- Issue date Jul 10, 2018
- eSilicon Corporation
- Javier DeLaCruz
- G01 - MEASURING TESTING
Information Patent Grant
Communication interface architecture using serializer/deserializer
- Patent number 9,984,997
- Issue date May 29, 2018
- eSilicon Corporation
- Javier DeLaCruz
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel signal via structure
- Patent number 9,461,000
- Issue date Oct 4, 2016
- eSilicon Corporation
- Javier DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Testing of thru-silicon vias
- Patent number 9,435,846
- Issue date Sep 6, 2016
- eSilicon Corporation
- Javier DeLaCruz
- G01 - MEASURING TESTING
Information Patent Grant
Mixed-sized pillars that are probeable and routable
- Patent number 9,263,409
- Issue date Feb 16, 2016
- eSilicon Corporation
- Javier DeLaCruz
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
ELONGATED PAD STRUCTURE
- Publication number 20160163669
- Publication date Jun 9, 2016
- eSilicon Corporation
- Javier DeLaCruz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WIRELESS PROBES
- Publication number 20160161554
- Publication date Jun 9, 2016
- eSilicon Corporation
- Javier DeLaCruz
- G01 - MEASURING TESTING
Information Patent Application
Communication Interface Architecture Using Serializer/Deserializer
- Publication number 20160027482
- Publication date Jan 28, 2016
- eSilicon Corporation
- Javier DeLaCruz
- G11 - INFORMATION STORAGE
Information Patent Application
Testing of Thru-Silicon Vias
- Publication number 20140347089
- Publication date Nov 27, 2014
- eSilicon Corporation
- Javier DeLaCruz
- G01 - MEASURING TESTING
Information Patent Application
Mixed-Sized Pillars That Are Probeable and Routable
- Publication number 20140346513
- Publication date Nov 27, 2014
- eSilicon Corporation
- Javier DeLaCruz
- G01 - MEASURING TESTING
Information Patent Application
Parallel Signal Via Structure
- Publication number 20140346678
- Publication date Nov 27, 2014
- eSilicon Corporation
- Javier DeLaCruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Internal package interconnect with electrically parallel vias
- Publication number 20040000709
- Publication date Jan 1, 2004
- Javier Delacruz
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR