TREA

Javier Mauricio OLARTE GONZALEZ

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  • Campinas, BR
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Patents Grantslast 30 patents

  • Information Patent Grant

    Back bias regulator circuit and method therefor
    • Patent number 10,394,264
    • Issue date Aug 27, 2019
    • NXP USA, INC.
    • Ricardo Pureza Coimbra
    • G05 - CONTROLLING REGULATING
  • Information Patent Grant

    Sample-and-hold circuit
    • Patent number 9,997,254
    • Issue date Jun 12, 2018
    • NXP USA, INC.
    • André Luis Vilas Boas
    • G05 - CONTROLLING REGULATING
  • Information Patent Grant

    Sample and hold circuit
    • Patent number 9,984,763
    • Issue date May 29, 2018
    • NXP USA, INC.
    • Andre Luis Vilas Boas
    • H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

  • Information Patent Application

    BACK BIAS REGULATOR CIRCUIT AND METHOD THEREFOR
    • Publication number 20190250656
    • Publication date Aug 15, 2019
    • NXP USA, Inc.
    • Ricardo Pureza Coimbra
    • G05 - CONTROLLING REGULATING
  • Information Patent Application

    SAMPLE AND HOLD CIRCUIT
    • Publication number 20180151242
    • Publication date May 31, 2018
    • NXP USA, Inc.
    • Andre Luis Vilas Boas
    • H03 - BASIC ELECTRONIC CIRCUITRY
  • Information Patent Application

    Sample-and-Hold Circuit
    • Publication number 20180019020
    • Publication date Jan 18, 2018
    • FREESCALE SEMICONDUCTOR, INC.
    • André Luis VILAS BOAS
    • G11 - INFORMATION STORAGE