Jay Kuhn

Person

Seattle, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
RFID tag clock frequency reduction during tuning
- Patent number 11,853,826
- Issue date Dec 26, 2023
- Impinj, Inc.
- John D. Hyde
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rectifier backflow reduction via biasing
- Patent number 11,734,540
- Issue date Aug 22, 2023
- Impinj, Inc.
- Amita Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RFID tag rectifiers with bias current reuse
- Patent number 11,481,591
- Issue date Oct 25, 2022
- Impinj, Inc.
- Charles J. T. Peach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rectifier backflow reduction via biasing
- Patent number 11,188,803
- Issue date Nov 30, 2021
- Impinj, Inc.
- Amita Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RFID tag clock frequency reduction during tuning
- Patent number 10,929,734
- Issue date Feb 23, 2021
- Impinj, Inc.
- John D. Hyde
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Impedance-change mitigation in RFID tags
- Patent number 10,885,417
- Issue date Jan 5, 2021
- Impinj, Inc.
- Theron Stanford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RFID tag rectifiers with bias current reuse
- Patent number 10,713,549
- Issue date Jul 14, 2020
- Impinj, Inc.
- Charles J. T. Peach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Impedance-change mitigation in RFID tags
- Patent number 10,572,789
- Issue date Feb 25, 2020
- Impinj, Inc.
- Theron Stanford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-tuning of RFID tags using nonuniform impedance steps
- Patent number RE47755
- Issue date Dec 3, 2019
- Impinj, Inc.
- John Hyde
Information Patent Grant
RFID tag clock frequency reduction during tuning
- Patent number 10,445,535
- Issue date Oct 15, 2019
- Impinj, Inc.
- John D. Hyde
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RFID tag clock frequency reduction during tuning
- Patent number 10,002,266
- Issue date Jun 19, 2018
- Impinj, Inc.
- John D. Hyde
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Impedance-change mitigation in RFID tags
- Patent number 9,886,658
- Issue date Feb 6, 2018
- Impinj, Inc.
- Theron Stanford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RFID tag memory check using wireless margin read commands
- Patent number 9,607,191
- Issue date Mar 28, 2017
- Impinj, Inc.
- Charles Peach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self tuning RFID tags
- Patent number 9,349,090
- Issue date May 24, 2016
- Impinj, Inc.
- Shailendra Srinivas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-tuning of RFID tags using nonuniform impedance steps
- Patent number 9,087,282
- Issue date Jul 21, 2015
- Impinj, Inc.
- John Hyde
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hot RF rectifiers for RFID applications
- Patent number 9,000,835
- Issue date Apr 7, 2015
- Impinj, Inc.
- Charles Peach
- G05 - CONTROLLING REGULATING
Information Patent Grant
Self tuning RFID tags
- Patent number 8,952,792
- Issue date Feb 10, 2015
- Impinj, Inc.
- Shailendra Srinivas
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
RFID tag with MOS bipolar hybrid rectifier
- Patent number 8,326,256
- Issue date Dec 4, 2012
- Impinj, Inc.
- Jay A. Kuhn
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Voltage regulators using a resistive chain to bias a native transistor
- Patent number 8,072,329
- Issue date Dec 6, 2011
- Impinj, Inc.
- Shailendra Srinivas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage reference circuit with low-power bandgap
- Patent number 7,808,387
- Issue date Oct 5, 2010
- Impinj, Inc.
- Jay A. Kuhn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic on-die defect isolation
- Patent number 7,667,231
- Issue date Feb 23, 2010
- Impinj, Inc.
- John D. Hyde
- G01 - MEASURING TESTING
Information Patent Grant
Circuit and method for implementing a low supply voltage current re...
- Patent number 7,394,308
- Issue date Jul 1, 2008
- Cypress Semiconductor Corp.
- Jonathon C. Stiff
- G05 - CONTROLLING REGULATING
Information Patent Grant
Wafer level testing for RFID tags
- Patent number 7,312,622
- Issue date Dec 25, 2007
- Impinj, Inc.
- John D. Hyde
- G01 - MEASURING TESTING
Information Patent Grant
RFID tag design with circuitry for wafer level testing
- Patent number 7,307,528
- Issue date Dec 11, 2007
- Impinj, Inc.
- Robert M. Glidden
- G01 - MEASURING TESTING
Information Patent Grant
Capacitive level shifting for analog signal processing
- Patent number 7,233,274
- Issue date Jun 19, 2007
- Impinj, Inc.
- Jay A. Kuhn
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for correction of differential signal path delays in a PLL
- Patent number 6,975,695
- Issue date Dec 13, 2005
- Cypress Semiconductor Corp.
- Jay A. Kuhn
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Master/dual-slave D type flip-flop
- Patent number 6,617,901
- Issue date Sep 9, 2003
- Cypress Semiconductor Corp.
- Jay A. Kuhn
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual differential input comparators with integrated phase detector
- Patent number 6,617,883
- Issue date Sep 9, 2003
- Cypress Semiconductor Corp.
- Jay A. Kuhn
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Automatic on-die defect isolation
- Publication number 20070172966
- Publication date Jul 26, 2007
- John D. Hyde
- G01 - MEASURING TESTING
Information Patent Application
CAPACITIVE LEVEL SHIFTING FOR ANALOG SIGNAL PROCESSING
- Publication number 20070139244
- Publication date Jun 21, 2007
- Impinj, Inc.
- Jay A. Kuhn
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RFID tag design with circuitry for wafer level testing
- Publication number 20060125505
- Publication date Jun 15, 2006
- Robert M. Glidden
- G01 - MEASURING TESTING
Information Patent Application
Wafer level testing for RFID tags
- Publication number 20060125507
- Publication date Jun 15, 2006
- John D. Hyde
- G01 - MEASURING TESTING

Person

Patents Grantslast 30 patents

RFID tag clock frequency reduction during tuning

Rectifier backflow reduction via biasing

RFID tag rectifiers with bias current reuse

Rectifier backflow reduction via biasing

RFID tag clock frequency reduction during tuning

Impedance-change mitigation in RFID tags

RFID tag rectifiers with bias current reuse

Impedance-change mitigation in RFID tags

Self-tuning of RFID tags using nonuniform impedance steps

RFID tag clock frequency reduction during tuning

RFID tag clock frequency reduction during tuning

Impedance-change mitigation in RFID tags

RFID tag memory check using wireless margin read commands

Self tuning RFID tags

Self-tuning of RFID tags using nonuniform impedance steps

Hot RF rectifiers for RFID applications

Self tuning RFID tags

RFID tag with MOS bipolar hybrid rectifier

Voltage regulators using a resistive chain to bias a native transistor

Voltage reference circuit with low-power bandgap

Automatic on-die defect isolation

Circuit and method for implementing a low supply voltage current re...

Wafer level testing for RFID tags

RFID tag design with circuitry for wafer level testing

Capacitive level shifting for analog signal processing

Circuit for correction of differential signal path delays in a PLL

Master/dual-slave D type flip-flop

Dual differential input comparators with integrated phase detector

Patents Applicationslast 30 patents

Automatic on-die defect isolation

CAPACITIVE LEVEL SHIFTING FOR ANALOG SIGNAL PROCESSING

RFID tag design with circuitry for wafer level testing

Wafer level testing for RFID tags