Jay Madhukar Shah

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Bangalore, IN

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Patents Grantslast 30 patents

Information Patent Grant
Flip-flop with reduced retention voltage
- Patent number 9,673,786
- Issue date Jun 6, 2017
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Stacked common gate finFET devices for area optimization
- Patent number 9,397,101
- Issue date Jul 19, 2016
- QUALCOMM Incorporated
- HariKrishna Chintarlapalli Reddy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adaptive standard cell architecture and layout techniques for low a...
- Patent number 9,070,552
- Issue date Jun 30, 2015
- QUALCOMM Incorporated
- Jay Madhukar Shah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit and layout techniques for flop tray area and power otimization
- Patent number 9,024,658
- Issue date May 5, 2015
- QUALCOMM Incorporated
- Jay Madhukar Shah
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
STACKED COMMON GATE FINFET DEVICES FOR AREA OPTIMIZATION
- Publication number 20150255461
- Publication date Sep 10, 2015
- QUALCOMM Incorporated
- HariKrishna CHINTARLAPALLI REDDY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT AND LAYOUT TECHNIQUES FOR FLOP TRAY AREA AND POWER OTIMIZATION
- Publication number 20140359385
- Publication date Dec 4, 2014
- QUALCOMM Incorporated
- Jay Madhukar Shah
- G01 - MEASURING TESTING
Information Patent Application
FLIP-FLOP WITH REDUCED RETENTION VOLTAGE
- Publication number 20140306735
- Publication date Oct 16, 2014
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
AREA EFFICIENT GRIDDED POLYSILICON LAYOUTS
- Publication number 20130032885
- Publication date Feb 7, 2013
- QUALCOMM Incorporated
- Chethan Swamynathan
- H01 - BASIC ELECTRIC ELEMENTS