Jay Patel

Person

Los Gatos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Partitioned memory with shared memory resources and configurable fu...
- Patent number 11,221,764
- Issue date Jan 11, 2022
- MoSys, Inc.
- Michael J Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for randomizer
- Patent number 9,971,567
- Issue date May 15, 2018
- MoSys, Inc.
- Michael J Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable partitionable counter
- Patent number 9,667,546
- Issue date May 30, 2017
- MoSys, Inc.
- Michael Morrison
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for randomizer
- Patent number 9,529,569
- Issue date Dec 27, 2016
- MoSys, Inc.
- Michael J Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory with bank-conflict-resolution (BCR) module including cache
- Patent number 9,496,009
- Issue date Nov 15, 2016
- MoSys, Inc.
- Dipak Sikdar
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with background built-in self-repair using background...
- Patent number 9,361,196
- Issue date Jun 7, 2016
- MoSys, Inc.
- Bendik Kleveland
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system including variable write burst and broadcast command...
- Patent number 9,354,823
- Issue date May 31, 2016
- MoSys, Inc.
- Michael J Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data synchronization for circuit resources without using a resource...
- Patent number 9,118,611
- Issue date Aug 25, 2015
- MoSys, Inc.
- Jay Patel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory device with background built-in self-testing and background...
- Patent number 9,037,928
- Issue date May 19, 2015
- MoSys, Inc.
- Bendik Kleveland
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing latency in serializer-deserializer links
- Patent number 8,832,336
- Issue date Sep 9, 2014
- MoSys, Inc.
- Michael J. Morrison
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for parsing frames
- Patent number 8,824,468
- Issue date Sep 2, 2014
- Agate Logic, Inc.
- Malcolm J. Wing
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory system including variable write command scheduling
- Patent number 8,635,417
- Issue date Jan 21, 2014
- MoSys, Inc.
- Michael J. Morrison
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing latency in serializer-deserializer links
- Patent number 8,527,676
- Issue date Sep 3, 2013
- MoSys, Inc.
- Michael J. Morrison
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system including variable write command scheduling
- Patent number 8,473,695
- Issue date Jun 25, 2013
- MoSys, Inc.
- Michael J. Morrison
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communication interface and protocol
- Patent number 8,370,725
- Issue date Feb 5, 2013
- MoSys, Inc.
- Michael J. Miller
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for parsing frames
- Patent number 8,050,262
- Issue date Nov 1, 2011
- Agate Logic, Inc.
- Malcolm J. Wing
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for parsing frames
- Patent number 7,773,595
- Issue date Aug 10, 2010
- Agate Logic, Inc.
- Malcolm J. Wing
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Heterogeneous configurable integrated circuit
- Patent number 7,557,605
- Issue date Jul 7, 2009
- Cswitch Corporation
- Godfrey P. D'Souza
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Method and Apparatus for Randomizer
- Publication number 20170109135
- Publication date Apr 20, 2017
- MoSys, Inc.
- Michael J. MILLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Main Memory And Coprocessor With Low Latency
- Publication number 20160188222
- Publication date Jun 30, 2016
- MoSys, Inc.
- Michael J. MILLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Main Memory And Coprocessor With Low Latency
- Publication number 20160188481
- Publication date Jun 30, 2016
- MoSys, Inc.
- Michael J. MILLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Randomizer
- Publication number 20160019029
- Publication date Jan 21, 2016
- MoSys, Inc.
- Michael J. MILLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTITIONED MEMORY WITH SHARED MEMORY RESOURCES AND CONFIGURABLE FU...
- Publication number 20150019803
- Publication date Jan 15, 2015
- MoSys, Inc.
- Michael J Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-REPAIR USING BACKGROUND...
- Publication number 20140317460
- Publication date Oct 23, 2014
- MoSys, Inc.
- Bendik Kleveland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY WITH BANK-CONFLICT-RESOLUTION (BCR) MODULE INCLUDING CACHE
- Publication number 20130332665
- Publication date Dec 12, 2013
- MoSys, Inc.
- Dipak Sikdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE PARTITIONABLE COUNTER
- Publication number 20130332708
- Publication date Dec 12, 2013
- Michael Morrison
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL COUNTER
- Publication number 20130329555
- Publication date Dec 12, 2013
- Jay Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM INCLUDING VARIABLE WRITE BURST AND BROADCAST COMMAND...
- Publication number 20130332681
- Publication date Dec 12, 2013
- Michael J. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAFFIC METERING AND SHAPING FOR NETWORK PACKETS
- Publication number 20130329553
- Publication date Dec 12, 2013
- Mankit Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-TESTING AND BACKGROUND...
- Publication number 20130173970
- Publication date Jul 4, 2013
- MoSys, Inc.
- Bendik Kleveland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM INCLUDING VARIABLE WRITE COMMAND SCHEDULING
- Publication number 20120254558
- Publication date Oct 4, 2012
- Michael J. Morrison
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM INCLUDING VARIABLE WRITE COMMAND SCHEDULING
- Publication number 20120254562
- Publication date Oct 4, 2012
- Michael J. Morrison
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing Latency In Serializer-Deserializer Links
- Publication number 20120221882
- Publication date Aug 30, 2012
- MoSys, Inc.
- Michael J. Morrison
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Data Synchronization For Circuit Resources Without Using A Resource...
- Publication number 20120047260
- Publication date Feb 23, 2012
- MoSys, Inc.
- Jay Patel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and Method for Parsing Frames
- Publication number 20110317720
- Publication date Dec 29, 2011
- AGATE LOGIC, INC.
- Malcolm J. Wing
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
COMMUNICATION INTERFACE AND PROTOCOL
- Publication number 20110191647
- Publication date Aug 4, 2011
- Michael J. Miller
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Reducing Latency in Serializer-Deserializer Links
- Publication number 20110191619
- Publication date Aug 4, 2011
- MoSys Inc.
- Michael J. Morrison
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and Method for Parsing Frames
- Publication number 20100329262
- Publication date Dec 30, 2010
- Agate Logic, Inc., a Delaware Corporation
- Malcolm J. Wing
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD FOR PARSING FRAMES
- Publication number 20090073970
- Publication date Mar 19, 2009
- Cswitch Corporation
- Malcolm J. Wing
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUIT
- Publication number 20090072858
- Publication date Mar 19, 2009
- Cswitch Corporation
- Godfrey P. D'Souza
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Partitioned memory with shared memory resources and configurable fu...

Method and apparatus for randomizer

Programmable partitionable counter

Method and apparatus for randomizer

Memory with bank-conflict-resolution (BCR) module including cache

Memory device with background built-in self-repair using background...

Memory system including variable write burst and broadcast command...

Data synchronization for circuit resources without using a resource...

Memory device with background built-in self-testing and background...

Reducing latency in serializer-deserializer links

System and method for parsing frames

Memory system including variable write command scheduling

Reducing latency in serializer-deserializer links

Memory system including variable write command scheduling

Communication interface and protocol

System and method for parsing frames

System and method for parsing frames

Heterogeneous configurable integrated circuit

Patents Applicationslast 30 patents

Method and Apparatus for Randomizer

Integrated Main Memory And Coprocessor With Low Latency

Integrated Main Memory And Coprocessor With Low Latency

Method and Apparatus for Randomizer

PARTITIONED MEMORY WITH SHARED MEMORY RESOURCES AND CONFIGURABLE FU...

MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-REPAIR USING BACKGROUND...

MEMORY WITH BANK-CONFLICT-RESOLUTION (BCR) MODULE INCLUDING CACHE

PROGRAMMABLE PARTITIONABLE COUNTER

DUAL COUNTER

MEMORY SYSTEM INCLUDING VARIABLE WRITE BURST AND BROADCAST COMMAND...

TRAFFIC METERING AND SHAPING FOR NETWORK PACKETS

MEMORY DEVICE WITH BACKGROUND BUILT-IN SELF-TESTING AND BACKGROUND...

MEMORY SYSTEM INCLUDING VARIABLE WRITE COMMAND SCHEDULING

MEMORY SYSTEM INCLUDING VARIABLE WRITE COMMAND SCHEDULING

Reducing Latency In Serializer-Deserializer Links

Data Synchronization For Circuit Resources Without Using A Resource...

System and Method for Parsing Frames

COMMUNICATION INTERFACE AND PROTOCOL

Reducing Latency in Serializer-Deserializer Links

System and Method for Parsing Frames

SYSTEM AND METHOD FOR PARSING FRAMES

HETEROGENEOUS CONFIGURABLE INTEGRATED CIRCUIT