Membership
Tour
Register
Log in
Jayabrata Ghosh Dastidar
Follow
Person
Santa Clara, CA, US
People
Overview
Industries
Organizations
People
Information
Impact
Patents Grants
last 30 patents
Information
Patent Grant
Test techniques and circuitry
Patent number
9,021,323
Issue date
Apr 28, 2015
Altera Corporation
Jayabrata Gosh Dastidar
G01 - MEASURING TESTING
Information
Patent Grant
Method and apparatus for die testing
Patent number
8,952,713
Issue date
Feb 10, 2015
Altera Corporation
Jayabrata Ghosh Dastidar
G01 - MEASURING TESTING
Information
Patent Grant
Integrated circuit with configurable test pins
Patent number
8,327,199
Issue date
Dec 4, 2012
Altera Corporation
Jayabrata Ghosh Dastidar
G01 - MEASURING TESTING
Information
Patent Grant
Area-efficient memory built-in-self-test circuitry with advanced de...
Patent number
8,259,522
Issue date
Sep 4, 2012
Altera Corporation
Jayabrata Ghosh Dastidar
G11 - INFORMATION STORAGE
Information
Patent Grant
Area-efficient memory built-in-self-test circuitry with advanced de...
Patent number
8,004,915
Issue date
Aug 23, 2011
Altera Corporation
Jayabrata Ghosh Dastidar
G11 - INFORMATION STORAGE
Information
Patent Grant
Method and apparatus for routing efficient built-in self test for o...
Patent number
7,707,472
Issue date
Apr 27, 2010
Altera Corporation
Jayabrata Ghosh Dastidar
G11 - INFORMATION STORAGE
Information
Patent Grant
Pipelined scan structures for testing embedded cores
Patent number
7,502,979
Issue date
Mar 10, 2009
Altera Corporation
Jayabrata Ghosh Dastidar
G01 - MEASURING TESTING
Information
Patent Grant
Automatic test configuration generation facilitating repair of prog...
Patent number
7,409,669
Issue date
Aug 5, 2008
Altera Corporation
Jayabrata Ghosh Dastidar
G01 - MEASURING TESTING
Information
Patent Grant
Constraint-driven test generation for programmable logic device int...
Patent number
7,373,621
Issue date
May 13, 2008
Altera Corporation
Jayabrata Ghosh Dastidar
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Soft error tolerance for configuration memory in programmable devices
Patent number
7,339,816
Issue date
Mar 4, 2008
Altera Corporation
Jayabrata Ghosh Dastidar
G11 - INFORMATION STORAGE
Information
Patent Grant
Apparatus and method for encrypting security sensitive data
Patent number
7,299,390
Issue date
Nov 20, 2007
Altera Corporation
Jayabrata Ghosh Dastidar
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Method and apparatus for monitoring yield of integrated circuits
Patent number
7,212,032
Issue date
May 1, 2007
Altera Corporation
Jayabrata Ghosh Dastidar
G01 - MEASURING TESTING
Information
Patent Grant
Automatic testing for programmable networks of control signals
Patent number
7,131,043
Issue date
Oct 31, 2006
Altera Corporation
Jayabrata Ghosh Dastidar
G01 - MEASURING TESTING
Information
Patent Grant
Failure isolation and repair techniques for integrated circuits
Patent number
7,111,213
Issue date
Sep 19, 2006
Altera Corporation
Jayabrata Ghosh Dastidar
G01 - MEASURING TESTING
Information
Patent Grant
Techniques for providing early failure warning of a programmable ci...
Patent number
7,062,685
Issue date
Jun 13, 2006
Altera Corporation
Jordan Plofsky
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and apparatus for application specific test of PLDs
Patent number
7,058,534
Issue date
Jun 6, 2006
Altera Corporation
Paul Tracy
G01 - MEASURING TESTING
Information
Patent Grant
Techniques for automatically generating tests for programmable circ...
Patent number
7,024,327
Issue date
Apr 4, 2006
Altera Corporation
Jayabrata Ghosh Dastidar
G01 - MEASURING TESTING
Patents Applications
last 30 patents
Information
Patent Application
Pipelined scan structures for testing embedded cores
Publication number
20060282729
Publication date
Dec 14, 2006
Altera Corporation
Jayabrata Ghosh Dastidar
G01 - MEASURING TESTING