Jayabrata Ghosh Dastidar

Person

Campbell, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Clock control circuitry and methods of utilizing the clock control...
- Patent number 9,075,112
- Issue date Jul 7, 2015
- Altera Corporation
- Kalyana Ravindra Kantipudi
- G01 - MEASURING TESTING
Information Patent Grant
Clock control circuitry and methods of utilizing the clock control...
- Patent number 8,621,303
- Issue date Dec 31, 2013
- Altera Corporation
- Kalyana Ravindra Kantipudi
- G01 - MEASURING TESTING
Information Patent Grant
Automatic test pattern generation system for programmable logic dev...
- Patent number 8,516,322
- Issue date Aug 20, 2013
- Altera Corporation
- Jayabrata Ghosh Dastidar
- G01 - MEASURING TESTING
Information Patent Grant
Logic circuit testing with reduced overhead
- Patent number 7,996,743
- Issue date Aug 9, 2011
- Altera Corporation
- Tze Sin Tan
- G01 - MEASURING TESTING
Information Patent Grant
Testing circuitry for programmable logic devices with selectable po...
- Patent number 7,571,413
- Issue date Aug 4, 2009
- Altera Corporation
- Jayabrata Ghosh Dastidar
- G01 - MEASURING TESTING
Information Patent Grant
Configurable built in self test circuitry for testing memory arrays
- Patent number 7,475,315
- Issue date Jan 6, 2009
- Altera Corporation
- Balaji Natarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for testing integrated circuits
- Patent number 7,424,658
- Issue date Sep 9, 2008
- Altera Corporation
- Jayabrata Ghosh Dastidar
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for bit mapping memories in programmable logic...
- Patent number 7,266,028
- Issue date Sep 4, 2007
- Altera Corporation
- Jayabrata Ghosh Dastidar
- G11 - INFORMATION STORAGE

Jayabrata Ghosh Dastidar

Person

Patents Grantslast 30 patents

Clock control circuitry and methods of utilizing the clock control...

Clock control circuitry and methods of utilizing the clock control...

Automatic test pattern generation system for programmable logic dev...

Logic circuit testing with reduced overhead

Testing circuitry for programmable logic devices with selectable po...

Configurable built in self test circuitry for testing memory arrays

Method and apparatus for testing integrated circuits

Method and apparatus for bit mapping memories in programmable logic...