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Jayanta Bahadra
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Austin, TX, US
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last 30 patents
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Patent Grant
Integrated circuit design verification through forced clock glitches
Patent number
9,043,737
Issue date
May 26, 2015
FREESCALE SEMICONDUCTOR, INC.
Jayanta Bahadra
G06 - COMPUTING CALCULATING COUNTING
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last 30 patents
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Patent Application
Integrated Circuit Design Verification Through Forced Clock Glitches
Publication number
20140325463
Publication date
Oct 30, 2014
FREESCALE SEMICONDUCTOR, INC.
Jayanta Bahadra
G06 - COMPUTING CALCULATING COUNTING