Jayanthi Pallinti

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Alternate pad structures/passivation inegration schemes to reduce o...
- Patent number 8,552,560
- Issue date Oct 8, 2013
- LSI Corporation
- Hemanshu Bhatt
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Reduction of macro level stresses in copper/low-K wafers
- Patent number 8,076,779
- Issue date Dec 13, 2011
- LSI Corporation
- Sey-Shing Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Eliminate IMC cracking in post wirebonded dies: macro level stress...
- Patent number 7,531,442
- Issue date May 12, 2009
- LSI Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduce or eliminate IMC cracking in post wire bonded dies by doping...
- Patent number 7,205,673
- Issue date Apr 17, 2007
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal planarization system
- Patent number 6,951,808
- Issue date Oct 4, 2005
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND...
- Patent number 6,838,379
- Issue date Jan 4, 2005
- LSI Logic Corporation
- Byung-Sung Kwak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrochemical planarization end point detection
- Patent number 6,752,916
- Issue date Jun 22, 2004
- LSI Logic Corporation
- Yan Fang
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Process for planarization of integrated circuit structure which inh...
- Patent number 6,713,394
- Issue date Mar 30, 2004
- LSI Logic Corporation
- Ronald J. Nagahara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming planarized isolation trench in integrated circu...
- Patent number 6,607,967
- Issue date Aug 19, 2003
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal planarization system
- Patent number 6,586,326
- Issue date Jul 1, 2003
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arrangement and method for polishing a surface of a semiconductor w...
- Patent number 6,555,475
- Issue date Apr 29, 2003
- LSI Logic Corporation
- Jayanthi Pallinti
- B24 - GRINDING POLISHING
Information Patent Grant
Process for selective polishing of metal-filled trenches of integra...
- Patent number 6,503,828
- Issue date Jan 7, 2003
- LSI Logic Corporation
- Ronald J. Nagahara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for planarization of integrated circuit structure which inh...
- Patent number 6,489,242
- Issue date Dec 3, 2002
- LSI Logic Corporation
- Ronald J. Nagahara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arrangement and method for polishing a surface of a semiconductor w...
- Patent number 6,439,981
- Issue date Aug 27, 2002
- LSI Logic Corporation
- Jayanthi Pallinti
- B24 - GRINDING POLISHING
Information Patent Grant
Shallow trench isolation chemical-mechanical polishing process
- Patent number 6,424,019
- Issue date Jul 23, 2002
- LSI Logic Corporation
- Shouli Steve Hsia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for planarization of metal-filled trenches of integrated ci...
- Patent number 6,417,093
- Issue date Jul 9, 2002
- LSI Logic Corporation
- James J. Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for CMP removal of excess trench or via filler metal which...
- Patent number 6,391,768
- Issue date May 21, 2002
- LSI Logic Corporation
- Dawn M. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for CMP endpoint detection
- Patent number 6,372,524
- Issue date Apr 16, 2002
- LSI Logic Corporation
- James J. Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for shallow trench isolations with chemical-mechanical polis...
- Patent number 6,060,370
- Issue date May 9, 2000
- LSI Logic Corporation
- Shouli Steve Hsia
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
ALTERNATE PAD STRUCTURES/PASSIVATION INTEGRATION SCHEMES TO REDUCE...
- Publication number 20140030541
- Publication date Jan 30, 2014
- LSI Corporation
- Hemanshu Bhatt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL ELECTRONICS PACKAGE
- Publication number 20100244276
- Publication date Sep 30, 2010
- LSI Corporation
- Jeffrey P. Burleson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Eliminate IMC cracking in post wirebonded dies: macro level stress...
- Publication number 20070123024
- Publication date May 31, 2007
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Alternate pad structures/passivation inegration schemes to reduce o...
- Publication number 20070114667
- Publication date May 24, 2007
- LSI Logic Corporation
- Hemanshu Bhatt
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Reduction of macro level stresses in copper/Low-K wafers by alterin...
- Publication number 20070102812
- Publication date May 10, 2007
- LSI Logic Corporation
- Sey-Shing Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for improved local planarity control during electropolishing
- Publication number 20050224358
- Publication date Oct 13, 2005
- LSI Logic Corporation
- Byung-Sung Kwak
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
Method of fabricating an alloy cap layer over CU wires to improve e...
- Publication number 20040207093
- Publication date Oct 21, 2004
- Sey-Shing Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metal planarization system
- Publication number 20040018719
- Publication date Jan 29, 2004
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for planarization of integrated circuit structure which inh...
- Publication number 20030017704
- Publication date Jan 23, 2003
- Ronald J. Nagahara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metal planarization system
- Publication number 20020132470
- Publication date Sep 19, 2002
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS

Jayanthi Pallinti

Person

Patents Grantslast 30 patents

Alternate pad structures/passivation inegration schemes to reduce o...

Reduction of macro level stresses in copper/low-K wafers

Eliminate IMC cracking in post wirebonded dies: macro level stress...

Reduce or eliminate IMC cracking in post wire bonded dies by doping...

Metal planarization system

PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND...

Electrochemical planarization end point detection

Process for planarization of integrated circuit structure which inh...

Process for forming planarized isolation trench in integrated circu...

Metal planarization system

Arrangement and method for polishing a surface of a semiconductor w...

Process for selective polishing of metal-filled trenches of integra...

Process for planarization of integrated circuit structure which inh...

Arrangement and method for polishing a surface of a semiconductor w...

Shallow trench isolation chemical-mechanical polishing process

Process for planarization of metal-filled trenches of integrated ci...

Process for CMP removal of excess trench or via filler metal which...

Method for CMP endpoint detection

Method for shallow trench isolations with chemical-mechanical polis...

Patents Applicationslast 30 patents

ALTERNATE PAD STRUCTURES/PASSIVATION INTEGRATION SCHEMES TO REDUCE...

THREE-DIMENSIONAL ELECTRONICS PACKAGE

Eliminate IMC cracking in post wirebonded dies: macro level stress...

Alternate pad structures/passivation inegration schemes to reduce o...

Reduction of macro level stresses in copper/Low-K wafers by alterin...

Method for improved local planarity control during electropolishing

Method of fabricating an alloy cap layer over CU wires to improve e...

Metal planarization system

Process for planarization of integrated circuit structure which inh...

Metal planarization system