JAYASEKHAR THOLIYIL

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Hillsboro, OR, US

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Patents Grantslast 30 patents

Information Patent Grant
Logging errors in error handling devices in a system
- Patent number 10,802,903
- Issue date Oct 13, 2020
- Intel Corporation
- Sivakumar Radhakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Micro-architectural techniques to minimize companion die firmware l...
- Patent number 10,496,565
- Issue date Dec 3, 2019
- Intel Corporation
- Anand K. Enamandram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Robust memory link testing using memory controller
- Patent number 8,868,992
- Issue date Oct 21, 2014
- Intel Corporation
- Bryan L. Spry
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MICRO-ARCHITECTURAL TECHNIQUES TO MINIMIZE COMPANION DIE FIRMWARE L...
- Publication number 20190042514
- Publication date Feb 7, 2019
- Intel Corporation
- Anand K. ENAMANDRAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGGING ERRORS IN ERROR HANDLING DEVICES IN A SYSTEM
- Publication number 20190034264
- Publication date Jan 31, 2019
- Intel Corporation
- Sivakumar RADHAKRISHNAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROBUST MEMORY LINK TESTING USING MEMORY CONTROLLER
- Publication number 20110161752
- Publication date Jun 30, 2011
- BRYAN L. SPRY
- G11 - INFORMATION STORAGE