Jaydeep P. Kulkarni

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Nanoscale-aligned three-dimensional stacked integrated circuit
- Patent number 12,094,775
- Issue date Sep 17, 2024
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanofabrication and design techniques for 3D ICs and configurable A...
- Patent number 12,079,557
- Issue date Sep 3, 2024
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Catalyst influenced chemical etching for fabricating three-dimensio...
- Patent number 11,881,435
- Issue date Jan 23, 2024
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanoscale-aligned three-dimensional stacked integrated circuit
- Patent number 11,600,525
- Issue date Mar 7, 2023
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Current steering level-shifter
- Patent number 11,489,526
- Issue date Nov 1, 2022
- Intel Corporation
- Andres Malavasi Mora
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Catalyst influenced chemical etching for fabricating three-dimensio...
- Patent number 11,355,397
- Issue date Jun 7, 2022
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for reducing di/dt
- Patent number 11,079,830
- Issue date Aug 3, 2021
- Intel Corporation
- Jaydeep P. Kulkarni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems to selectively boost an operating voltage of, a...
- Patent number 10,984,855
- Issue date Apr 20, 2021
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Grant
System, apparatus and method for reducing voltage swing on an inter...
- Patent number 10,762,877
- Issue date Sep 1, 2020
- Intel Corporation
- Anupama A. Thaploo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast Fourier transform architecture
- Patent number 10,713,333
- Issue date Jul 14, 2020
- Apple Inc.
- Farhana Sheikh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low swing bitline for sensing arrays
- Patent number 10,685,688
- Issue date Jun 16, 2020
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Grant
Current steering level-shifter
- Patent number 10,666,259
- Issue date May 26, 2020
- Intel Corporation
- Andres Malavasi Mora
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bi-directional multi-mode charge pump
- Patent number 10,511,224
- Issue date Dec 17, 2019
- Intel Corporation
- Jaydeep Kulkarni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digitally trimmable integrated resistors including resistive memory...
- Patent number 10,347,309
- Issue date Jul 9, 2019
- Intel Corporation
- Jaydeep P. Kulkarni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Aging aware dynamic keeper apparatus and associated method
- Patent number 10,269,419
- Issue date Apr 23, 2019
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage level shifter monitor with tunable voltage level shifter re...
- Patent number 10,243,563
- Issue date Mar 26, 2019
- Intel Corporation
- Andrea Bonetti
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and systems to selectively boost an operating voltage of, a...
- Patent number 10,217,509
- Issue date Feb 26, 2019
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device including encoded data line-multiplexer
- Patent number 10,217,495
- Issue date Feb 26, 2019
- Intel Corporation
- Jaydeep Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Grant
Retention minimum voltage determination techniques
- Patent number 10,199,091
- Issue date Feb 5, 2019
- Intel Corporation
- Minki Cho
- G11 - INFORMATION STORAGE
Information Patent Grant
Low swing bitline for sensing arrays
- Patent number 10,199,080
- Issue date Feb 5, 2019
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive voltage system for aging guard-band reduction
- Patent number 10,122,347
- Issue date Nov 6, 2018
- Intel Corporation
- Minki Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bi-directional multi-mode charge pump
- Patent number 10,014,767
- Issue date Jul 3, 2018
- Intel Corporation
- Jaydeep Kulkarni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Capacitive wordline boosting
- Patent number 10,002,654
- Issue date Jun 19, 2018
- Intel Corporation
- Jaydeep P Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus for charge recovery during low power mode
- Patent number 9,948,179
- Issue date Apr 17, 2018
- Intel Corporation
- Jaydeep P. Kulkarni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reduced swing bit-line apparatus and method
- Patent number 9,947,388
- Issue date Apr 17, 2018
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device including encoded data line-multiplexer
- Patent number 9,905,278
- Issue date Feb 27, 2018
- Intel Corporation
- Jaydeep Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Grant
Resilient register file circuit for dynamic variation tolerance and...
- Patent number 9,772,903
- Issue date Sep 26, 2017
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Grant
Register files including distributed capacitor circuit blocks
- Patent number 9,767,858
- Issue date Sep 19, 2017
- Intel Corporation
- Hamid-Reza S. Bonakdar
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for reducing di/dt during power wake-up
- Patent number 9,755,631
- Issue date Sep 5, 2017
- Intel Corporation
- Yong Shim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Assist circuit for memory
- Patent number 9,685,208
- Issue date Jun 20, 2017
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY WITH CHARGE SHARING BITLINES
- Publication number 20240428851
- Publication date Dec 26, 2024
- Intel Corporation
- Amlan GHOSH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT
- Publication number 20240429099
- Publication date Dec 26, 2024
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY ARRAY UTILIZING BITCELLS WITH SINGLE-ENDED READ CIRCUITRY
- Publication number 20240118826
- Publication date Apr 11, 2024
- Intel Corporation
- Amlan Ghosh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PORTED MEMORY ARRAY UTILIZING BITCELLS WITH BALANCED P-N DIFF...
- Publication number 20240005982
- Publication date Jan 4, 2024
- Amlan Ghosh
- G11 - INFORMATION STORAGE
Information Patent Application
NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...
- Publication number 20230419010
- Publication date Dec 28, 2023
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...
- Publication number 20230124676
- Publication date Apr 20, 2023
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...
- Publication number 20230118578
- Publication date Apr 20, 2023
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT
- Publication number 20230116581
- Publication date Apr 13, 2023
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CATALYST INFLUENCED CHEMICAL ETCHING FOR FABRICATING THREE-DIMENSIO...
- Publication number 20220270930
- Publication date Aug 25, 2022
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT
- Publication number 20210366771
- Publication date Nov 25, 2021
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...
- Publication number 20210350061
- Publication date Nov 11, 2021
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CATALYST INFLUENCED CHEMICAL ETCHING FOR FABRICATING THREE-DIMENSIO...
- Publication number 20200365464
- Publication date Nov 19, 2020
- Board of Regents, The University of Texas System
- Sidlgata V. Sreenivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CURRENT STEERING LEVEL-SHIFTER
- Publication number 20200358443
- Publication date Nov 12, 2020
- Intel Corporation
- Andres Malavasi Mora
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND SYSTEMS TO SELECTIVELY BOOST AN OPERATING VOLTAGE OF, A...
- Publication number 20190362777
- Publication date Nov 28, 2019
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Application
LOW SWING BITLINE FOR SENSING ARRAYS
- Publication number 20190206456
- Publication date Jul 4, 2019
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Application
AGING AWARE DYNAMIC KEEPER APPARATUS AND ASSOCIATED METHOD
- Publication number 20180342289
- Publication date Nov 29, 2018
- Intel Corporation
- Jaydeep P. KULKARNI
- G11 - INFORMATION STORAGE
Information Patent Application
FAST FOURIER TRANSFORM ARCHITECTURE
- Publication number 20180336161
- Publication date Nov 22, 2018
- Intel Corporation
- Farhana SHEIKH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Reducing Voltage Swing On An Inter...
- Publication number 20180301120
- Publication date Oct 18, 2018
- Anupama A. Thaploo
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Application
LOW SWING BITLINE FOR SENSING ARRAYS
- Publication number 20180294019
- Publication date Oct 11, 2018
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE VOLTAGE SYSTEM FOR AGING GUARD-BAND REDUCTION
- Publication number 20180287592
- Publication date Oct 4, 2018
- Intel Corporation
- Minki Cho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BI-DIRECTIONAL MULTI-MODE CHARGE PUMP
- Publication number 20180226887
- Publication date Aug 9, 2018
- Intel Corporation
- Jaydeep Kulkarni
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
VOLTAGE LEVEL SHIFTER MONITOR WITH TUNABLE VOLTAGE LEVEL SHIFTER RE...
- Publication number 20180191347
- Publication date Jul 5, 2018
- Intel Corporation
- Andrea Bonetti
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RETENTION MINIMUM VOLTAGE DETERMINATION TECHNIQUES
- Publication number 20180166145
- Publication date Jun 14, 2018
- Intel Corporation
- Minki CHO
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE INCLUDING ENCODED DATA LINE-MULTIPLEXER
- Publication number 20180130509
- Publication date May 10, 2018
- Intel Corporation
- Jaydeep Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR REDUCING di/dt
- Publication number 20170344090
- Publication date Nov 30, 2017
- Jaydeep P. Kulkarni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BI-DIRECTIONAL MULTI-MODE CHARGE PUMP
- Publication number 20170279348
- Publication date Sep 28, 2017
- Jaydeep Kulkarni
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
REDUCED SWING BIT-LINE APPARATUS AND METHOD
- Publication number 20170270998
- Publication date Sep 21, 2017
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND SYSTEMS TO SELECTIVELY BOOST AN OPERATING VOLTAGE OF, A...
- Publication number 20170243637
- Publication date Aug 24, 2017
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Application
DIGITALLY TRIMMABLE INTEGRATED RESISTORS INCLUDING RESISTIVE MEMORY...
- Publication number 20170229161
- Publication date Aug 10, 2017
- Intel Corporation
- Jaydeep P. Kulkarni
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR REDUCING di/dt DURING POWER WAKE-UP
- Publication number 20170149427
- Publication date May 25, 2017
- Intel Corporation
- Yong Shim
- H03 - BASIC ELECTRONIC CIRCUITRY

Jaydeep P. Kulkarni

Person

Patents Grantslast 30 patents

Nanoscale-aligned three-dimensional stacked integrated circuit

Nanofabrication and design techniques for 3D ICs and configurable A...

Catalyst influenced chemical etching for fabricating three-dimensio...

Nanoscale-aligned three-dimensional stacked integrated circuit

Current steering level-shifter

Catalyst influenced chemical etching for fabricating three-dimensio...

Apparatus and method for reducing di/dt

Methods and systems to selectively boost an operating voltage of, a...

System, apparatus and method for reducing voltage swing on an inter...

Fast Fourier transform architecture

Low swing bitline for sensing arrays

Current steering level-shifter

Bi-directional multi-mode charge pump

Digitally trimmable integrated resistors including resistive memory...

Aging aware dynamic keeper apparatus and associated method

Voltage level shifter monitor with tunable voltage level shifter re...

Methods and systems to selectively boost an operating voltage of, a...

Memory device including encoded data line-multiplexer

Retention minimum voltage determination techniques

Low swing bitline for sensing arrays

Adaptive voltage system for aging guard-band reduction

Bi-directional multi-mode charge pump

Capacitive wordline boosting

Apparatus for charge recovery during low power mode

Reduced swing bit-line apparatus and method

Memory device including encoded data line-multiplexer

Resilient register file circuit for dynamic variation tolerance and...

Register files including distributed capacitor circuit blocks

Apparatus and method for reducing di/dt during power wake-up

Assist circuit for memory

Patents Applicationslast 30 patents

MEMORY WITH CHARGE SHARING BITLINES

NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT

MEMORY ARRAY UTILIZING BITCELLS WITH SINGLE-ENDED READ CIRCUITRY

MULTI-PORTED MEMORY ARRAY UTILIZING BITCELLS WITH BALANCED P-N DIFF...

NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...

NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...

NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...

NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT

CATALYST INFLUENCED CHEMICAL ETCHING FOR FABRICATING THREE-DIMENSIO...

NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT

NANOFABRICATION AND DESIGN TECHNIQUES FOR 3D ICS AND CONFIGURABLE A...

CATALYST INFLUENCED CHEMICAL ETCHING FOR FABRICATING THREE-DIMENSIO...

CURRENT STEERING LEVEL-SHIFTER

METHODS AND SYSTEMS TO SELECTIVELY BOOST AN OPERATING VOLTAGE OF, A...

LOW SWING BITLINE FOR SENSING ARRAYS

AGING AWARE DYNAMIC KEEPER APPARATUS AND ASSOCIATED METHOD

FAST FOURIER TRANSFORM ARCHITECTURE

System, Apparatus And Method For Reducing Voltage Swing On An Inter...

LOW SWING BITLINE FOR SENSING ARRAYS

ADAPTIVE VOLTAGE SYSTEM FOR AGING GUARD-BAND REDUCTION

BI-DIRECTIONAL MULTI-MODE CHARGE PUMP

VOLTAGE LEVEL SHIFTER MONITOR WITH TUNABLE VOLTAGE LEVEL SHIFTER RE...

RETENTION MINIMUM VOLTAGE DETERMINATION TECHNIQUES

MEMORY DEVICE INCLUDING ENCODED DATA LINE-MULTIPLEXER

APPARATUS AND METHOD FOR REDUCING di/dt

BI-DIRECTIONAL MULTI-MODE CHARGE PUMP

REDUCED SWING BIT-LINE APPARATUS AND METHOD

METHODS AND SYSTEMS TO SELECTIVELY BOOST AN OPERATING VOLTAGE OF, A...

DIGITALLY TRIMMABLE INTEGRATED RESISTORS INCLUDING RESISTIVE MEMORY...

APPARATUS AND METHOD FOR REDUCING di/dt DURING POWER WAKE-UP