Jayen J. Desai

Person

Wellington, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus for a monotonic delay line, method for fast locking of a...
- Patent number 9,628,092
- Issue date Apr 18, 2017
- Intel Corporation
- Erin D. Francom
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for a monotonic delay line, method for fast locking of a...
- Patent number 9,178,502
- Issue date Nov 3, 2015
- Intel Corporation
- Erin D. Francom
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital clock placement engine apparatus and method with duty cycle...
- Patent number 9,124,257
- Issue date Sep 1, 2015
- Intel Corporation
- Jayen J. Desai
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock recovery
- Patent number 7,873,132
- Issue date Jan 18, 2011
- Hewlett-Packard Development Company, L.P.
- Jayen Desai
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
On-chip circuitry for bus validation
- Patent number 7,610,526
- Issue date Oct 27, 2009
- Hewlett-Packard Development Company, L.P.
- Derek A. Sherlock
- G01 - MEASURING TESTING
Information Patent Grant
Interpolator systems with linearity adjustments and related methods
- Patent number 7,498,858
- Issue date Mar 3, 2009
- Hewlett-Packard Development Company, L.P.
- Jayen J. Desai
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
On-die impedance calibration
- Patent number 7,391,221
- Issue date Jun 24, 2008
- Hewlett-Packard Development Company, L.P.
- Jayen J. Desai
- G01 - MEASURING TESTING
Information Patent Grant
Clock signal generation using digital frequency synthesizer
- Patent number 7,276,952
- Issue date Oct 2, 2007
- Hewlett-Packard Development Company, L.P.
- Jayen J. Desai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latching annihilation based logic gate
- Patent number 6,583,650
- Issue date Jun 24, 2003
- Hewlett-Packard Development Company
- Samuel D Naffziger
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Latching annihilation based logic gate
- Patent number 6,459,304
- Issue date Oct 1, 2002
- Hewlett-Packard Company
- Samuel D Naffziger
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CLOCK INTERPOLATION SYSTEM FOR EYE-CENTERING
- Publication number 20220393672
- Publication date Dec 8, 2022
- Jayen Desai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS FOR A MONOTONIC DELAY LINE, METHOD FOR FAST LOCKING OF A...
- Publication number 20150372684
- Publication date Dec 24, 2015
- Erin D. FRANCOM
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS FOR A MONOTONIC DELAY LINE, METHOD FOR FAST LOCKING OF A...
- Publication number 20150188527
- Publication date Jul 2, 2015
- Erin D. FRANCOM
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIGITAL CLOCK PLACEMENT ENGINE APPARATUS AND METHOD WITH DUTY CYCLE...
- Publication number 20140203851
- Publication date Jul 24, 2014
- Jayen J. Desai
- G11 - INFORMATION STORAGE
Information Patent Application
Clock signal generation using digital frequency synthesizer
- Publication number 20070096789
- Publication date May 3, 2007
- Jayen J. Desai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock recovery
- Publication number 20070064848
- Publication date Mar 22, 2007
- Jayen Desai
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
On-die impedance calibration
- Publication number 20070013395
- Publication date Jan 18, 2007
- Jayen J. Desai
- G01 - MEASURING TESTING
Information Patent Application
On-chip circuitry for bus validation
- Publication number 20060168483
- Publication date Jul 27, 2006
- Derek A. Sherlock
- G01 - MEASURING TESTING
Information Patent Application
Interpolator systems and methods
- Publication number 20060091925
- Publication date May 4, 2006
- Jayen J. Desai
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Bi-directional transmission line termination system
- Publication number 20030062921
- Publication date Apr 3, 2003
- David J. C. Johnson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Latching annihilation based logic gate
- Publication number 20020030512
- Publication date Mar 14, 2002
- Samuel D. Naffziger
- H03 - BASIC ELECTRONIC CIRCUITRY

Jayen J. Desai

Person

Patents Grantslast 30 patents

Apparatus for a monotonic delay line, method for fast locking of a...

Apparatus for a monotonic delay line, method for fast locking of a...

Digital clock placement engine apparatus and method with duty cycle...

Clock recovery

On-chip circuitry for bus validation

Interpolator systems with linearity adjustments and related methods

On-die impedance calibration

Clock signal generation using digital frequency synthesizer

Latching annihilation based logic gate

Latching annihilation based logic gate

Patents Applicationslast 30 patents

CLOCK INTERPOLATION SYSTEM FOR EYE-CENTERING

APPARATUS FOR A MONOTONIC DELAY LINE, METHOD FOR FAST LOCKING OF A...

APPARATUS FOR A MONOTONIC DELAY LINE, METHOD FOR FAST LOCKING OF A...

DIGITAL CLOCK PLACEMENT ENGINE APPARATUS AND METHOD WITH DUTY CYCLE...

Clock signal generation using digital frequency synthesizer

Clock recovery

On-die impedance calibration

On-chip circuitry for bus validation

Interpolator systems and methods

Bi-directional transmission line termination system

Latching annihilation based logic gate