Jayesh Gaur

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Instruction and micro-architecture support for decompression on core
- Patent number 12,182,018
- Issue date Dec 31, 2024
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compressed cache memory with decompress on fault
- Patent number 12,130,738
- Issue date Oct 29, 2024
- Intel Corporation
- Vedvyas Shanbhogue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device, method and system to predict an address collision by a load...
- Patent number 12,086,591
- Issue date Sep 10, 2024
- Intel Corporation
- Sudhanshu Shukla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Application programming interface for fine grained low latency deco...
- Patent number 12,028,094
- Issue date Jul 2, 2024
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for hardware-based memoization of function cal...
- Patent number 12,020,033
- Issue date Jun 25, 2024
- Intel Corporation
- Niranjan Kumar Soundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data relocation for inline metadata
- Patent number 11,972,126
- Issue date Apr 30, 2024
- Intel Corporation
- David M. Durham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technology for dynamically tuning processor features
- Patent number 11,656,971
- Issue date May 23, 2023
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detecting a dynamic control flow re-convergence point for condition...
- Patent number 11,645,078
- Issue date May 9, 2023
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cryptographic computing engine for memory load and store units of a...
- Patent number 11,575,504
- Issue date Feb 7, 2023
- Intel Corporation
- David M. Durham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technology for dynamically tuning processor features
- Patent number 11,256,599
- Issue date Feb 22, 2022
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level system memory with near memory capable of storing compr...
- Patent number 11,188,467
- Issue date Nov 30, 2021
- Intel Corporation
- Israel Diamand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High bandwidth destructive read embedded memory
- Patent number 11,043,256
- Issue date Jun 22, 2021
- Intel Corporation
- Kaushik Vaidyanathan
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for mitigating dram cache conflicts through har...
- Patent number 10,956,327
- Issue date Mar 23, 2021
- Intel Corporation
- Adithya Nallan Chakravarthi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technology for dynamically tuning processor features
- Patent number 10,915,421
- Issue date Feb 9, 2021
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory aware reordered source
- Patent number 10,866,902
- Issue date Dec 15, 2020
- Intel Corporation
- Ishwar S. Bhati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for focused data value prediction to a...
- Patent number 10,846,093
- Issue date Nov 24, 2020
- Intel Corporation
- Sumeet Bandishte
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-efficient last level cache architecture
- Patent number 10,776,270
- Issue date Sep 15, 2020
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic predication of hard-to-predict convergent branches
- Patent number 10,754,655
- Issue date Aug 25, 2020
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Criticality based port scheduling
- Patent number 10,719,355
- Issue date Jul 21, 2020
- Intel Corporation
- Pooja Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient hardware-based extraction of program instructions for cri...
- Patent number 10,496,413
- Issue date Dec 3, 2019
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write congestion aware bypass for non-volatile memory, last level c...
- Patent number 10,331,582
- Issue date Jun 25, 2019
- Intel Corporation
- Ishwar S. Bhati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for prefetch-aware replacement in a ca...
- Patent number 10,268,600
- Issue date Apr 23, 2019
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using data pattern to mark cache lines as invalid
- Patent number 10,176,099
- Issue date Jan 8, 2019
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-efficient last level cache architecture
- Patent number 10,162,756
- Issue date Dec 25, 2018
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partner-aware virtual microsectoring for sectored cache architectures
- Patent number 10,013,352
- Issue date Jul 3, 2018
- Intel Corporation
- Sreenivas Subramoney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Online learning based algorithms to increase retention and reuse of...
- Patent number 9,720,829
- Issue date Aug 1, 2017
- Intel Corporation
- Suresh Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data compression in processor caches
- Patent number 9,251,096
- Issue date Feb 2, 2016
- Intel Corporation
- Sreenivas Subramoney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bypass and insertion algorithms for exclusive last-level caches
- Patent number 8,667,222
- Issue date Mar 4, 2014
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INSTRUCTION ELIMINATION THROUGH HARDWARE DRIVEN MEMOIZATION OF LOOP...
- Publication number 20240103874
- Publication date Mar 28, 2024
- Intel Corporation
- Niranjan Kumar Soundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHORT PIPELINE FOR FAST RECOVERY FROM A BRANCH MISPREDICTION
- Publication number 20240103878
- Publication date Mar 28, 2024
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Register File Prefetch
- Publication number 20230214325
- Publication date Jul 6, 2023
- Intel Corporation
- SUDHANSHU SHUKLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE, METHOD AND SYSTEM TO PROVIDE A PREDICTED VALUE WITH A SEQUE...
- Publication number 20230195465
- Publication date Jun 22, 2023
- Intel Corporation
- Stanislav Shwartsman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE, METHOD, AND SYSTEM TO FACILITATE IMPROVED BANDWIDTH OF A BR...
- Publication number 20230195469
- Publication date Jun 22, 2023
- Intel Corporation
- Sumeet Bandishte
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, APPARATUS AND METHOD FOR THROTTLING FUSION OF MICRO-OPERATI...
- Publication number 20230195456
- Publication date Jun 22, 2023
- Intel Corporation
- Sufiyan Syed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE, METHOD AND SYSTEM TO PREDICT AN ADDRESS COLLISION BY A LOAD...
- Publication number 20220308876
- Publication date Sep 29, 2022
- Intel Corporation
- Sudhanshu Shukla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR HARDWARE-BASED MEMOIZATION OF FUNCTION CAL...
- Publication number 20220206816
- Publication date Jun 30, 2022
- Intel Corporation
- Niranjan Kumar Soundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technology For Dynamically Tuning Processor Features
- Publication number 20220206925
- Publication date Jun 30, 2022
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSED CACHE MEMORY WITH DECOMPRESS ON FAULT
- Publication number 20220197793
- Publication date Jun 23, 2022
- Intel Corporation
- Vedvyas Shanbhogue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLICATION PROGRAMMING INTERFACE FOR FINE GRAINED LOW LATENCY DECO...
- Publication number 20220197659
- Publication date Jun 23, 2022
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECULATIVE DECOMPRESSION WITHIN PROCESSOR CORE CACHES
- Publication number 20220197643
- Publication date Jun 23, 2022
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Micro-Architecture Support for Decompression on Core
- Publication number 20220197799
- Publication date Jun 23, 2022
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLICATION PROGRAMMING INTERFACE FOR FINE GRAINED LOW LATENCY DECO...
- Publication number 20220197813
- Publication date Jun 23, 2022
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH CONFIDENCE MULTIPLE BRANCH OFFSET PREDICTOR
- Publication number 20220129763
- Publication date Apr 28, 2022
- Intel Corporation
- Sumeet Bandishte
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA RELOCATION FOR INLINE METADATA
- Publication number 20210405896
- Publication date Dec 30, 2021
- Intel Corporation
- David M. Durham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technology For Dynamically Tuning Processor Features
- Publication number 20210109839
- Publication date Apr 15, 2021
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL SYSTEM MEMORY WITH NEAR MEMORY CAPABLE OF STORING COMPR...
- Publication number 20210056030
- Publication date Feb 25, 2021
- Intel Corporation
- Israel DIAMAND
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETECTING A DYNAMIC CONTROL FLOW RE-CONVERGENCE POINT FOR CONDITION...
- Publication number 20210019149
- Publication date Jan 21, 2021
- Intel Corporation
- ADARSH CHAUHAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR MITIGATING DRAM CACHE CONFLICTS THROUGH HAR...
- Publication number 20200409849
- Publication date Dec 31, 2020
- Intel Corporation
- Adithya NALLAN CHAKRAVARTHI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH BANDWIDTH DESTRUCTIVE READ EMBEDDED MEMORY
- Publication number 20200411079
- Publication date Dec 31, 2020
- Intel Corporation
- Kaushik Vaidyanathan
- G11 - INFORMATION STORAGE
Information Patent Application
System, Apparatus And Method For Focused Data Value Prediction To A...
- Publication number 20200201644
- Publication date Jun 25, 2020
- Intel Corporation
- Sumeet Bandishte
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRYPTOGRAPHIC COMPUTING ENGINE FOR MEMORY LOAD AND STORE UNITS OF A...
- Publication number 20200169383
- Publication date May 28, 2020
- Intel Corporation
- David M. Durham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC PREDICATION OF HARD-TO-PREDICT CONVERGENT BRANCHES
- Publication number 20200004542
- Publication date Jan 2, 2020
- Intel Corporation
- Adarsh Chauhan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Adaptively Buffering Write Data In...
- Publication number 20190286567
- Publication date Sep 19, 2019
- Intel Corporation
- Mainak Chaudhuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRITICALITY BASED PORT SCHEDULING
- Publication number 20190243684
- Publication date Aug 8, 2019
- Intel Corporation
- Pooja Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-EFFICIENT LAST LEVEL CACHE ARCHITECTURE
- Publication number 20190243760
- Publication date Aug 8, 2019
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL SYSTEM MEMORY WITH NEAR MEMORY CAPABLE OF STORING COMPR...
- Publication number 20190095331
- Publication date Mar 28, 2019
- Intel Corporation
- Israel DIAMAND
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Prefetch-Aware Replacement In A Ca...
- Publication number 20190079877
- Publication date Mar 14, 2019
- Intel Corporation
- Jayesh Gaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR REDUCING WRITE CONGESTION IN NON-VOLATILE...
- Publication number 20180285268
- Publication date Oct 4, 2018
- Intel Corporation
- Kunal Kishore Korgaonkar
- G06 - COMPUTING CALCULATING COUNTING

Jayesh Gaur

Person

Patents Grantslast 30 patents

Instruction and micro-architecture support for decompression on core

Compressed cache memory with decompress on fault

Device, method and system to predict an address collision by a load...

Application programming interface for fine grained low latency deco...

Apparatus and method for hardware-based memoization of function cal...

Data relocation for inline metadata

Technology for dynamically tuning processor features

Detecting a dynamic control flow re-convergence point for condition...

Cryptographic computing engine for memory load and store units of a...

Technology for dynamically tuning processor features

Multi-level system memory with near memory capable of storing compr...

High bandwidth destructive read embedded memory

Systems and methods for mitigating dram cache conflicts through har...

Technology for dynamically tuning processor features

Memory aware reordered source

System, apparatus and method for focused data value prediction to a...

Memory-efficient last level cache architecture

Automatic predication of hard-to-predict convergent branches

Criticality based port scheduling

Efficient hardware-based extraction of program instructions for cri...

Write congestion aware bypass for non-volatile memory, last level c...

System, apparatus and method for prefetch-aware replacement in a ca...

Using data pattern to mark cache lines as invalid

Memory-efficient last level cache architecture

Partner-aware virtual microsectoring for sectored cache architectures

Online learning based algorithms to increase retention and reuse of...

Data compression in processor caches

Bypass and insertion algorithms for exclusive last-level caches

Patents Applicationslast 30 patents

INSTRUCTION ELIMINATION THROUGH HARDWARE DRIVEN MEMOIZATION OF LOOP...

SHORT PIPELINE FOR FAST RECOVERY FROM A BRANCH MISPREDICTION

Register File Prefetch

DEVICE, METHOD AND SYSTEM TO PROVIDE A PREDICTED VALUE WITH A SEQUE...

DEVICE, METHOD, AND SYSTEM TO FACILITATE IMPROVED BANDWIDTH OF A BR...

SYSTEM, APPARATUS AND METHOD FOR THROTTLING FUSION OF MICRO-OPERATI...

DEVICE, METHOD AND SYSTEM TO PREDICT AN ADDRESS COLLISION BY A LOAD...

APPARATUS AND METHOD FOR HARDWARE-BASED MEMOIZATION OF FUNCTION CAL...

Technology For Dynamically Tuning Processor Features

COMPRESSED CACHE MEMORY WITH DECOMPRESS ON FAULT

APPLICATION PROGRAMMING INTERFACE FOR FINE GRAINED LOW LATENCY DECO...

SPECULATIVE DECOMPRESSION WITHIN PROCESSOR CORE CACHES

Instruction and Micro-Architecture Support for Decompression on Core

APPLICATION PROGRAMMING INTERFACE FOR FINE GRAINED LOW LATENCY DECO...

HIGH CONFIDENCE MULTIPLE BRANCH OFFSET PREDICTOR

DATA RELOCATION FOR INLINE METADATA

Technology For Dynamically Tuning Processor Features

MULTI-LEVEL SYSTEM MEMORY WITH NEAR MEMORY CAPABLE OF STORING COMPR...

DETECTING A DYNAMIC CONTROL FLOW RE-CONVERGENCE POINT FOR CONDITION...

SYSTEMS AND METHODS FOR MITIGATING DRAM CACHE CONFLICTS THROUGH HAR...

HIGH BANDWIDTH DESTRUCTIVE READ EMBEDDED MEMORY

System, Apparatus And Method For Focused Data Value Prediction To A...

CRYPTOGRAPHIC COMPUTING ENGINE FOR MEMORY LOAD AND STORE UNITS OF A...

AUTOMATIC PREDICATION OF HARD-TO-PREDICT CONVERGENT BRANCHES

System, Apparatus And Method For Adaptively Buffering Write Data In...

CRITICALITY BASED PORT SCHEDULING

MEMORY-EFFICIENT LAST LEVEL CACHE ARCHITECTURE

MULTI-LEVEL SYSTEM MEMORY WITH NEAR MEMORY CAPABLE OF STORING COMPR...

System, Apparatus And Method For Prefetch-Aware Replacement In A Ca...

METHOD AND APPARATUS FOR REDUCING WRITE CONGESTION IN NON-VOLATILE...