Jayesh Iyer

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Performing partial register write operations in a processor
- Patent number 10,346,170
- Issue date Jul 9, 2019
- Intel Corporation
- Jayesh Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to do control speculation on loads in a high performance str...
- Patent number 10,241,789
- Issue date Mar 26, 2019
- Intel Corporation
- Alexander Y. Ostanevich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods to support counted loop exits in a multi-stra...
- Patent number 10,241,794
- Issue date Mar 26, 2019
- Intel Corporation
- Sergey P. Scherbinin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to create register windows for parallel iterat...
- Patent number 10,241,801
- Issue date Mar 26, 2019
- Intel Corporation
- Jayesh Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to efficiently handle allocation of memory ord...
- Patent number 10,235,171
- Issue date Mar 19, 2019
- Intel Corporation
- Alexander Y. Ostanevich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware apparatuses and methods to control access to a multiple ba...
- Patent number 9,471,501
- Issue date Oct 18, 2016
- Intel Corporation
- Andrey Kluchnikov
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHODS TO SUPPORT COUNTED LOOP EXITS IN A MULTI-STRA...
- Publication number 20180181400
- Publication date Jun 28, 2018
- Sergey P. Scherbinin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO CREATE REGISTER WINDOWS FOR PARALLEL ITERAT...
- Publication number 20180181405
- Publication date Jun 28, 2018
- Intel Corporation
- Jayesh IYER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO DO CONTROL SPECULATION ON LOADS IN A HIGH PERFORMANCE STR...
- Publication number 20180181396
- Publication date Jun 28, 2018
- Intel Corporation
- Alexander Y. OSTANEVICH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS OF DECOMPOSING LOOPS TO IMPROVE PERFORMANCE A...
- Publication number 20180181398
- Publication date Jun 28, 2018
- Intel Corporation
- Sergey P. Scherbinin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO EFFICIENTLY HANDLE ALLOCATION OF MEMORY ORD...
- Publication number 20180181397
- Publication date Jun 28, 2018
- Intel Corporation
- Alexander Y. OSTANEVICH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING PARTIAL REGISTER WRITE OPERATIONS IN A PROCESSOR
- Publication number 20160328239
- Publication date Nov 10, 2016
- Intel Corporation
- Jayesh Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING AND MAINTAINING A STACK OF PR...
- Publication number 20160179538
- Publication date Jun 23, 2016
- Intel Corporation
- JAMISON D. COLLINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE APPARATUSES AND METHODS TO CONTROL ACCESS TO A MULTIPLE BA...
- Publication number 20160092367
- Publication date Mar 31, 2016
- Intel Corporation
- Andrey Kluchnikov
- G06 - COMPUTING CALCULATING COUNTING

Jayesh Iyer

Person

Patents Grantslast 30 patents

Performing partial register write operations in a processor

Method to do control speculation on loads in a high performance str...

Apparatus and methods to support counted loop exits in a multi-stra...

Method and apparatus to create register windows for parallel iterat...

Method and apparatus to efficiently handle allocation of memory ord...

Hardware apparatuses and methods to control access to a multiple ba...

Patents Applicationslast 30 patents

APPARATUS AND METHODS TO SUPPORT COUNTED LOOP EXITS IN A MULTI-STRA...

METHOD AND APPARATUS TO CREATE REGISTER WINDOWS FOR PARALLEL ITERAT...

METHOD TO DO CONTROL SPECULATION ON LOADS IN A HIGH PERFORMANCE STR...

APPARATUS AND METHODS OF DECOMPOSING LOOPS TO IMPROVE PERFORMANCE A...

METHOD AND APPARATUS TO EFFICIENTLY HANDLE ALLOCATION OF MEMORY ORD...

PERFORMING PARTIAL REGISTER WRITE OPERATIONS IN A PROCESSOR

METHOD AND APPARATUS FOR IMPLEMENTING AND MAINTAINING A STACK OF PR...

HARDWARE APPARATUSES AND METHODS TO CONTROL ACCESS TO A MULTIPLE BA...