Jean-Charles Cote

Person

Montreal, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Efficient and flexible network for streaming data in circuits
- Patent number 10,788,530
- Issue date Sep 29, 2020
- Mentor Graphics Corporation
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Grant
Streaming networks efficiency using data throttling
- Patent number 10,775,436
- Issue date Sep 15, 2020
- Mentor Graphics Corporation
- Jean-Francois Cote
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data streaming for testing identical circuit blocks
- Patent number 10,473,721
- Issue date Nov 12, 2019
- Mentor Graphics Corporation
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Grant
Data generation for streaming networks in circuits
- Patent number 10,476,740
- Issue date Nov 12, 2019
- Mentor Graphics Corporation
- Jean-Francois Cote
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Test access architecture for multi-die circuits
- Patent number 9,389,944
- Issue date Jul 12, 2016
- Mentor Graphics Corporation
- Ronald Press
- G01 - MEASURING TESTING
Information Patent Grant
Test access architecture for stacked dies
- Patent number 9,389,945
- Issue date Jul 12, 2016
- Mentor Graphics Corporation
- Ronald Press
- G01 - MEASURING TESTING
Information Patent Grant
Efficient execution of color space processing functions in a graphi...
- Patent number 8,619,077
- Issue date Dec 31, 2013
- Matrox Graphics Inc.
- Jean-François Côté
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for at-speed testing of memory interface
- Patent number 8,516,317
- Issue date Aug 20, 2013
- Mentor Graphics Corporation
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for storing and distributing memory repair inf...
- Patent number 7,757,135
- Issue date Jul 13, 2010
- Mentor Graphics Corporation
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for at-speed testing of memory interface using scan
- Patent number 7,617,425
- Issue date Nov 10, 2009
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Clocking methodology for at-speed testing of scan circuits with syn...
- Patent number 7,424,656
- Issue date Sep 9, 2008
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Method and circuit for collecting memory failure information
- Patent number 7,370,251
- Issue date May 6, 2008
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock controller for at-speed testing of scan circuits
- Patent number 7,155,651
- Issue date Dec 26, 2006
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Efficient video processing method and system
- Patent number 7,129,962
- Issue date Oct 31, 2006
- Matrox Graphics Inc.
- Jean-Francois Côté
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification of embedded test structures in circuit designs
- Patent number 7,103,860
- Issue date Sep 5, 2006
- LogicVision, Inc.
- Paul Price
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Motion compensation using shared resources of a graphics processor...
- Patent number 6,952,211
- Issue date Oct 4, 2005
- Matrox Graphics Inc.
- Jean-Francois Côté
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and program product for designing hierarchical circuit for q...
- Patent number 6,868,532
- Issue date Mar 15, 2005
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Method of designing circuit having multiple test access ports, circ...
- Patent number 6,829,730
- Issue date Dec 7, 2004
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
System and method for converting adiabatic RF pulses into pseudo ad...
- Patent number 6,809,518
- Issue date Oct 26, 2004
- Gilles Beaudoin
- G01 - MEASURING TESTING
Information Patent Grant
Method for scan testing of digital circuit, digital circuit for use...
- Patent number 6,763,489
- Issue date Jul 13, 2004
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Test access circuit and method of accessing embedded test controlle...
- Patent number 6,760,874
- Issue date Jul 6, 2004
- LogicVision, Inc.
- Jean-Francois Côté
- G01 - MEASURING TESTING
Information Patent Grant
Method for collecting failure information for a memory using an emb...
- Patent number 6,738,938
- Issue date May 18, 2004
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and program product for completing a circuit design having e...
- Patent number 6,725,435
- Issue date Apr 20, 2004
- LogicVision, Inc.
- Jean-François Côté
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-contained embedded test design environment and environment set...
- Patent number 6,678,875
- Issue date Jan 13, 2004
- LogicVision, Inc.
- Brian John Pajak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan test method for providing real time identification of failing...
- Patent number 6,671,839
- Issue date Dec 30, 2003
- LogicVision, Inc.
- Jean-Francois Côté
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuitry for controlling clocks of embedded blocks duri...
- Patent number 6,614,263
- Issue date Sep 2, 2003
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Hierarchical design and test method and system, program product emb...
- Patent number 6,615,392
- Issue date Sep 2, 2003
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Fault insertion method, boundary scan cells, and integrated circuit...
- Patent number 6,536,008
- Issue date Mar 18, 2003
- Logic Vision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing high performance circuits
- Patent number 6,510,534
- Issue date Jan 21, 2003
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for controlling power level during BIST
- Patent number 6,330,681
- Issue date Dec 11, 2001
- LogicVision, Inc.
- Jean-François Cote
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR AT-SPEED TESTING OF MEMORY INTERFACE USING SCAN
- Publication number 20100037109
- Publication date Feb 11, 2010
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR STORING AND DISTRIBUTING MEMORY REPAIR INF...
- Publication number 20080065929
- Publication date Mar 13, 2008
- LogicVision, Inc.
- Benoit NADEAU-DOSTIE
- G11 - INFORMATION STORAGE
Information Patent Application
Method for at-speed testing of memory interface using scan
- Publication number 20070266278
- Publication date Nov 15, 2007
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
Insertion of embedded test in RTL to GDSII flow
- Publication number 20050273683
- Publication date Dec 8, 2005
- LogicVision, Inc.
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Application
Clocking methodology for at-speed testing of scan circuits with syn...
- Publication number 20050240790
- Publication date Oct 27, 2005
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Application
Masking circuit and method of masking corrupted bits
- Publication number 20050240848
- Publication date Oct 27, 2005
- LogicVision, Inc.
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Application
Clock controller for at-speed testing of scan circuits
- Publication number 20050240847
- Publication date Oct 27, 2005
- LogicVision, Inc.
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Application
Method and circuit for collecting memory failure information
- Publication number 20050047229
- Publication date Mar 3, 2005
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
Processor interface for test access port
- Publication number 20050028059
- Publication date Feb 3, 2005
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Application
SCAN TEST METHOD FOR PROVIDING REAL TIME IDENTIFICATION OF FAILING...
- Publication number 20040003329
- Publication date Jan 1, 2004
- Jean-Francois Cote
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for converting adiabatic RF pulses into pseudo ad...
- Publication number 20030234647
- Publication date Dec 25, 2003
- Corporation Du Centre De Recherche Du Centre Hospitalier De L'Universite De M...
- Gilles Beaudoin
- G01 - MEASURING TESTING
Information Patent Application
Method for collecting failure information for a memory using an emb...
- Publication number 20030226073
- Publication date Dec 4, 2003
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Application
Test access circuit and method of accessing embedded test controlle...
- Publication number 20030212524
- Publication date Nov 13, 2003
- Jean-Francois Cote
- G01 - MEASURING TESTING
Information Patent Application
Verification of embedded test structures in circuit designs
- Publication number 20030149949
- Publication date Aug 7, 2003
- Paul Price
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for licensing intellectual property circuits
- Publication number 20030149669
- Publication date Aug 7, 2003
- Michael C. Howells
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND CIRCUITRY FOR CONTROLLING CLOCKS OF EMBEDDED BLOCKS DURI...
- Publication number 20030146777
- Publication date Aug 7, 2003
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Application
Method and program product for completing a circuit design having e...
- Publication number 20030145297
- Publication date Jul 31, 2003
- Jean-Francois Cote
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Self-contained embedded test design envoronment and environment set...
- Publication number 20030145286
- Publication date Jul 31, 2003
- Brian John Pajak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and program product for designing hierarchical circuit for q...
- Publication number 20030110457
- Publication date Jun 12, 2003
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Application
Method of designing circuit having multiple test access ports, circ...
- Publication number 20020184562
- Publication date Dec 5, 2002
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING
Information Patent Application
Method for scan testing of digital circuit, digital circuit for use...
- Publication number 20020147951
- Publication date Oct 10, 2002
- Benoit Nadeau-Dostie
- G01 - MEASURING TESTING

Jean-Charles Cote

Person

Patents Grantslast 30 patents

Efficient and flexible network for streaming data in circuits

Streaming networks efficiency using data throttling

Data streaming for testing identical circuit blocks

Data generation for streaming networks in circuits

Test access architecture for multi-die circuits

Test access architecture for stacked dies

Efficient execution of color space processing functions in a graphi...

Methods for at-speed testing of memory interface

Method and apparatus for storing and distributing memory repair inf...

Method for at-speed testing of memory interface using scan

Clocking methodology for at-speed testing of scan circuits with syn...

Method and circuit for collecting memory failure information

Clock controller for at-speed testing of scan circuits

Efficient video processing method and system

Verification of embedded test structures in circuit designs

Motion compensation using shared resources of a graphics processor...

Method and program product for designing hierarchical circuit for q...

Method of designing circuit having multiple test access ports, circ...

System and method for converting adiabatic RF pulses into pseudo ad...

Method for scan testing of digital circuit, digital circuit for use...

Test access circuit and method of accessing embedded test controlle...

Method for collecting failure information for a memory using an emb...

Method and program product for completing a circuit design having e...

Self-contained embedded test design environment and environment set...

Scan test method for providing real time identification of failing...

Method and circuitry for controlling clocks of embedded blocks duri...

Hierarchical design and test method and system, program product emb...

Fault insertion method, boundary scan cells, and integrated circuit...

Method and apparatus for testing high performance circuits

Method and apparatus for controlling power level during BIST

Patents Applicationslast 30 patents

METHOD FOR AT-SPEED TESTING OF MEMORY INTERFACE USING SCAN

METHOD AND APPARATUS FOR STORING AND DISTRIBUTING MEMORY REPAIR INF...

Method for at-speed testing of memory interface using scan

Insertion of embedded test in RTL to GDSII flow

Clocking methodology for at-speed testing of scan circuits with syn...

Masking circuit and method of masking corrupted bits

Clock controller for at-speed testing of scan circuits

Method and circuit for collecting memory failure information

Processor interface for test access port

SCAN TEST METHOD FOR PROVIDING REAL TIME IDENTIFICATION OF FAILING...

System and method for converting adiabatic RF pulses into pseudo ad...

Method for collecting failure information for a memory using an emb...

Test access circuit and method of accessing embedded test controlle...

Verification of embedded test structures in circuit designs

Method and system for licensing intellectual property circuits

METHOD AND CIRCUITRY FOR CONTROLLING CLOCKS OF EMBEDDED BLOCKS DURI...

Method and program product for completing a circuit design having e...

Self-contained embedded test design envoronment and environment set...

Method and program product for designing hierarchical circuit for q...

Method of designing circuit having multiple test access ports, circ...

Method for scan testing of digital circuit, digital circuit for use...