Jean J. Audet

Person

Quebec, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Thin film capacitors for core and adjacent build up layers
- Patent number 11,388,821
- Issue date Jul 12, 2022
- International Business Machines Corporation
- Charles L. Arvin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Photonics package with face-to-face bonding
- Patent number 11,209,598
- Issue date Dec 28, 2021
- International Business Machines Corporation
- Barnim Alexander Janta-Polczynski
- G02 - OPTICS
Information Patent Grant
Semiconductor package floating metal checks
- Patent number 10,949,600
- Issue date Mar 16, 2021
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-density chip-to-chip interconnection with silicon bridge
- Patent number 10,784,202
- Issue date Sep 22, 2020
- International Business Machines Corporation
- Francois Arguin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Automated generation of surface-mount package design
- Patent number 10,706,204
- Issue date Jul 7, 2020
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-layer circuit using metal layers as a moisture diffusion barr...
- Patent number 10,687,420
- Issue date Jun 16, 2020
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Thin film capacitors for core and adjacent build up layers
- Patent number 10,660,209
- Issue date May 19, 2020
- International Business Machines Corporation
- Charles L. Arvin
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multi terminal capacitor within input output path of semiconductor...
- Patent number 10,622,299
- Issue date Apr 14, 2020
- International Business Machines Corporation
- Charles L. Arvin
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Interposer with lattice construction and embedded conductive metal...
- Patent number 10,460,956
- Issue date Oct 29, 2019
- International Business Machines Corporation
- Jean Audet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package floating metal checks
- Patent number 10,423,751
- Issue date Sep 24, 2019
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi terminal capacitor within input output path of semiconductor...
- Patent number 10,224,273
- Issue date Mar 5, 2019
- International Business Machines Corporation
- Charles L. Arvin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi terminal capacitor within input output path of semiconductor...
- Patent number 10,224,274
- Issue date Mar 5, 2019
- International Business Machines Corporation
- Charles L. Arvin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip assembly with connected component
- Patent number 10,211,174
- Issue date Feb 19, 2019
- International Business Machines Corporation
- Jean Audet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip assembly with connected component
- Patent number 9,984,988
- Issue date May 29, 2018
- International Business Machines Corporation
- Jean Audet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi terminal capacitor within input output path of semiconductor...
- Patent number 9,899,313
- Issue date Feb 20, 2018
- International Business Machines Corporation
- Charles L. Arvin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interposer with lattice construction and embedded conductive metal...
- Patent number 9,673,064
- Issue date Jun 6, 2017
- International Business Machines Corporation
- Jean Audet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip assembly with connected component
- Patent number 9,553,079
- Issue date Jan 24, 2017
- International Business Machines Corporation
- Jean Audet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interposer with lattice construction and embedded conductive metal...
- Patent number 9,443,799
- Issue date Sep 13, 2016
- International Business Machines Corporation
- Jean Audet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming coreless flip chip ball grid array (FCBGA) subst...
- Patent number 8,841,209
- Issue date Sep 23, 2014
- International Business Machines Corporation
- Sylvie Allard
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
High performance chip carrier substrate
- Patent number 7,886,435
- Issue date Feb 15, 2011
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor package having non-aligned active vias
- Patent number 7,868,459
- Issue date Jan 11, 2011
- International Business Machines Corporation
- Jean Audet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance chip carrier substrate
- Patent number 7,863,526
- Issue date Jan 4, 2011
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Apparatus for crack prevention in integrated circuit packages
- Patent number 7,786,579
- Issue date Aug 31, 2010
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Power grid structure to optimize performance of a multiple core pro...
- Patent number 7,667,470
- Issue date Feb 23, 2010
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for determining the impact of layer thicknesses on laminate...
- Patent number 7,482,180
- Issue date Jan 27, 2009
- International Business Machines Corporation
- Julien Sylvestre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance chip carrier substrate
- Patent number 7,454,833
- Issue date Nov 25, 2008
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Power grid structure to optimize performance of a multiple core pro...
- Patent number 7,420,378
- Issue date Sep 2, 2008
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced via structure for organic module performance
- Patent number 7,312,523
- Issue date Dec 25, 2007
- International Business Machines Corporation
- Jean J. Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Apparatus and method for customized burn-in of cores on a multicore...
- Patent number 7,268,570
- Issue date Sep 11, 2007
- International Business Machines Corporation
- Jean Audet
- G01 - MEASURING TESTING
Information Patent Grant
High performance chip carrier substrate
- Patent number 7,214,886
- Issue date May 8, 2007
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
PHOTONICS PACKAGE WITH FACE-TO-FACE BONDING
- Publication number 20200279840
- Publication date Sep 3, 2020
- International Business Machines Corporation
- BARNIM ALEXANDER JANTA-POLCZYNSKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN FILM CAPACITORS FOR CORE AND ADJACENT BUILD UP LAYERS
- Publication number 20200245466
- Publication date Jul 30, 2020
- International Business Machines Corporation
- Charles L. Arvin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AUTOMATED GENERATION OF SURFACE-MOUNT PACKAGE DESIGN
- Publication number 20200104454
- Publication date Apr 2, 2020
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS
- Publication number 20190362049
- Publication date Nov 28, 2019
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-DENSITY CHIP-TO-CHIP INTERCONNECTION WITH SILICON BRIDGE
- Publication number 20190172787
- Publication date Jun 6, 2019
- International Business Machines Corporation
- Francois Arguin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR...
- Publication number 20190172784
- Publication date Jun 6, 2019
- International Business Machines Corporation
- Charles L. Arvin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN FILM CAPACITORS FOR CORE AND ADJACENT BUILD UP LAYERS
- Publication number 20190150287
- Publication date May 16, 2019
- International Business Machines Corporation
- Charles L. Arvin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS
- Publication number 20190102505
- Publication date Apr 4, 2019
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR...
- Publication number 20180068945
- Publication date Mar 8, 2018
- International Business Machines Corporation
- Charles L. Arvin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR...
- Publication number 20180053717
- Publication date Feb 22, 2018
- International Business Machines Corporation
- Charles L. Arvin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR...
- Publication number 20180012838
- Publication date Jan 11, 2018
- International Business Machines Corporation
- Charles L. Arvin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP CHIP ASSEMBLY WITH CONNECTED COMPONENT
- Publication number 20170170133
- Publication date Jun 15, 2017
- International Business Machines Corporation
- JEAN AUDET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP CHIP ASSEMBLY WITH CONNECTED COMPONENT
- Publication number 20170170134
- Publication date Jun 15, 2017
- International Business Machines Corporation
- JEAN AUDET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL...
- Publication number 20160372337
- Publication date Dec 22, 2016
- International Business Machines Corporation
- Jean Audet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYER CIRCUIT USING METAL LAYERS AS A MOISTURE DIFFUSION BARR...
- Publication number 20160211481
- Publication date Jul 21, 2016
- Kyocera Circuit Solutions Inc.
- Jean AUDET
- G01 - MEASURING TESTING
Information Patent Application
MULTI-LAYER CIRCUIT USING METAL LAYERS AS A MOISTURE DIFFUSION BARR...
- Publication number 20160211229
- Publication date Jul 21, 2016
- Kyocera Circuit Solutions Inc.
- Jean AUDET
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYER CIRCUIT USING METAL LAYERS AS A MOISTURE DIFFUSION BARR...
- Publication number 20160210398
- Publication date Jul 21, 2016
- Kyocera Circuit Solutions Inc.
- Jean AUDET
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL...
- Publication number 20160172288
- Publication date Jun 16, 2016
- International Business Machines Corporation
- Jean Audet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL...
- Publication number 20160172290
- Publication date Jun 16, 2016
- International Business Machines Corporation
- Jean Audet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING CORELESS FLIP CHIP BALL GRID ARRAY (FCBGA) SUBST...
- Publication number 20130043060
- Publication date Feb 21, 2013
- International Business Machines Corporation
- Sylvie Allard
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
HIGH PERFORMANCE CHIP CARRIER SUBSTRATE
- Publication number 20080308923
- Publication date Dec 18, 2008
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
HIGH PERFORMANCE CHIP CARRIER SUBSTRATE
- Publication number 20080296054
- Publication date Dec 4, 2008
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
APPARATUS FOR CRACK PREVENTION IN INTEGRATED CIRCUIT PACKAGES
- Publication number 20080290510
- Publication date Nov 27, 2008
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Power Grid Structure to Optimize Performance of a Multiple Core Pro...
- Publication number 20080252308
- Publication date Oct 16, 2008
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR PACKAGE HAVING NON-ALIGNED ACTIVE VIAS
- Publication number 20080054482
- Publication date Mar 6, 2008
- Jean Audet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER GRID STRUCTURE TO OPTIMIZE PERFORMANCE OF A MULTIPLE CORE PRO...
- Publication number 20080012583
- Publication date Jan 17, 2008
- JEAN AUDET
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High performance chip carrier substrate
- Publication number 20070175658
- Publication date Aug 2, 2007
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
ENHANCED VIA STRUCTURE FOR ORGANIC MODULE PERFORMANCE
- Publication number 20070023913
- Publication date Feb 1, 2007
- International Business Machines Corporation
- Jean J. Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
High performance chip carrier substrate
- Publication number 20050109535
- Publication date May 26, 2005
- International Business Machines Corporation
- Jean Audet
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
AREA ARRAY PACKAGE WITH LOW INDUCTANCE CONNECTING DEVICE
- Publication number 20050013124
- Publication date Jan 20, 2005
- International Business Machines Corporation
- Jean Audet
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Jean J. Audet

Person

Patents Grantslast 30 patents

Thin film capacitors for core and adjacent build up layers

Photonics package with face-to-face bonding

Semiconductor package floating metal checks

High-density chip-to-chip interconnection with silicon bridge

Automated generation of surface-mount package design

Multi-layer circuit using metal layers as a moisture diffusion barr...

Thin film capacitors for core and adjacent build up layers

Multi terminal capacitor within input output path of semiconductor...

Interposer with lattice construction and embedded conductive metal...

Semiconductor package floating metal checks

Multi terminal capacitor within input output path of semiconductor...

Multi terminal capacitor within input output path of semiconductor...

Flip chip assembly with connected component

Flip chip assembly with connected component

Multi terminal capacitor within input output path of semiconductor...

Interposer with lattice construction and embedded conductive metal...

Flip chip assembly with connected component

Interposer with lattice construction and embedded conductive metal...

Method for forming coreless flip chip ball grid array (FCBGA) subst...

High performance chip carrier substrate

Semiconductor package having non-aligned active vias

High performance chip carrier substrate

Apparatus for crack prevention in integrated circuit packages

Power grid structure to optimize performance of a multiple core pro...

Method for determining the impact of layer thicknesses on laminate...

High performance chip carrier substrate

Power grid structure to optimize performance of a multiple core pro...

Enhanced via structure for organic module performance

Apparatus and method for customized burn-in of cores on a multicore...

High performance chip carrier substrate

Patents Applicationslast 30 patents

PHOTONICS PACKAGE WITH FACE-TO-FACE BONDING

THIN FILM CAPACITORS FOR CORE AND ADJACENT BUILD UP LAYERS

AUTOMATED GENERATION OF SURFACE-MOUNT PACKAGE DESIGN

SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS

HIGH-DENSITY CHIP-TO-CHIP INTERCONNECTION WITH SILICON BRIDGE

MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR...

THIN FILM CAPACITORS FOR CORE AND ADJACENT BUILD UP LAYERS

SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS

MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR...

MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR...

MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR...

FLIP CHIP ASSEMBLY WITH CONNECTED COMPONENT

FLIP CHIP ASSEMBLY WITH CONNECTED COMPONENT

INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL...

MULTI-LAYER CIRCUIT USING METAL LAYERS AS A MOISTURE DIFFUSION BARR...

MULTI-LAYER CIRCUIT USING METAL LAYERS AS A MOISTURE DIFFUSION BARR...

MULTI-LAYER CIRCUIT USING METAL LAYERS AS A MOISTURE DIFFUSION BARR...

INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL...

INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL...

METHOD FOR FORMING CORELESS FLIP CHIP BALL GRID ARRAY (FCBGA) SUBST...

HIGH PERFORMANCE CHIP CARRIER SUBSTRATE

HIGH PERFORMANCE CHIP CARRIER SUBSTRATE

APPARATUS FOR CRACK PREVENTION IN INTEGRATED CIRCUIT PACKAGES

Power Grid Structure to Optimize Performance of a Multiple Core Pro...

SEMICONDUCTOR PACKAGE HAVING NON-ALIGNED ACTIVE VIAS

POWER GRID STRUCTURE TO OPTIMIZE PERFORMANCE OF A MULTIPLE CORE PRO...

High performance chip carrier substrate

ENHANCED VIA STRUCTURE FOR ORGANIC MODULE PERFORMANCE

High performance chip carrier substrate

AREA ARRAY PACKAGE WITH LOW INDUCTANCE CONNECTING DEVICE