Jean-Jacques LECLER

Person

Antibes, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Dram-aware caching
- Patent number 11,520,706
- Issue date Dec 6, 2022
- QUALCOMM Incorporated
- Alain Artieri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory bank group interleaving
- Patent number 11,403,217
- Issue date Aug 2, 2022
- QUALCOMM Incorporated
- Alain Artieri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic memory scheduling routine with enhanced bank-group batching
- Patent number 11,126,431
- Issue date Sep 21, 2021
- QUALCOMM Incorporated
- Jean-Jacques Lecler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for ternary mapping
- Patent number 10,951,230
- Issue date Mar 16, 2021
- QUALCOMM Incorporated
- Jean-Jacques Lecler
- G11 - INFORMATION STORAGE
Information Patent Grant
Zero-latency network on chip (NoC)
- Patent number 9,882,839
- Issue date Jan 30, 2018
- QUALCOMM Incorporated
- Philippe Boucard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
DMA engine with STLB prefetch capabilities and tethered prefetching
- Patent number 9,465,749
- Issue date Oct 11, 2016
- QUALCOMM Technologies, Inc.
- Laurent Moll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three channel cache-coherency socket protocol
- Patent number 9,361,230
- Issue date Jun 7, 2016
- QUALCOMM Technologies, Inc.
- Jean-Jacques Lecler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System translation look-aside buffer with request-based allocation...
- Patent number 9,141,556
- Issue date Sep 22, 2015
- QUALCOMM Technologies, Inc.
- Laurent Moll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero-latency network on chip (NoC)
- Patent number 9,049,124
- Issue date Jun 2, 2015
- QUALCOMM Technologies, Inc.
- Jean-Jacques Lecler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Network on chip (NoC) with QoS features
- Patent number 8,316,171
- Issue date Nov 20, 2012
- Arteris S.A.
- Philippe Boucard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital delay device, digital oscillator clock signal generator and...
- Patent number 7,148,728
- Issue date Dec 12, 2006
- Arteris
- Luc Montperrus
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
DRAM-AWARE CACHING
- Publication number 20220350749
- Publication date Nov 3, 2022
- QUALCOMM Incorporated
- Alain ARTIERI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLED EARLY RESPONSE IN MASTER-SLAVE SYSTEMS
- Publication number 20220019459
- Publication date Jan 20, 2022
- QUALCOMM Incorporated
- Jean-Jacques LECLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCHEDULING MEMORY TRANSACTIONS
- Publication number 20210382651
- Publication date Dec 9, 2021
- QUALCOMM Incorporated
- Jean-Jacques LECLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BANK GROUP INTERLEAVING
- Publication number 20210133100
- Publication date May 6, 2021
- QUALCOMM Incorporated
- Alain ARTIERI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE CHANNEL CACHE-COHERENCY SOCKET PROTOCOL
- Publication number 20160011976
- Publication date Jan 14, 2016
- QUALCOMM TECHNOLOGIES INC.
- Jean-Jacques LECLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO-LATENCY NETWORK ON CHIP (NOC)
- Publication number 20150256486
- Publication date Sep 10, 2015
- QUALCOMM TECHNOLOGIES INC.
- Philippe BOUCARD
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM TRANSLATION LOOK-ASIDE BUFFER INTEGRATED IN AN INTERCONNECT
- Publication number 20140052919
- Publication date Feb 20, 2014
- Arteris SAS
- Laurent MOLL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM TRANSLATION LOOK-ASIDE BUFFER WITH REQUEST-BASED ALLOCATION...
- Publication number 20140052954
- Publication date Feb 20, 2014
- Arteris SAS
- Laurent MOLL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DMA ENGINE WITH STLB PREFETCH CAPABILITIES AND TETHERED PREFETCHING
- Publication number 20140052955
- Publication date Feb 20, 2014
- Arteris SAS
- Laurent MOLL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK ON CHIP (NOC) WITH QOS FEATURES
- Publication number 20130179613
- Publication date Jul 11, 2013
- ARTERIS S.A.
- Philippe Boucard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Access Latency Metering
- Publication number 20120290810
- Publication date Nov 15, 2012
- Jean-Jacques Lecler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK ON CHIP (NOC) WITH QOS FEATURES
- Publication number 20110302345
- Publication date Dec 8, 2011
- Philippe Boucard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Zero-latency network on chip (NoC)
- Publication number 20110085550
- Publication date Apr 14, 2011
- Jean-Jacques Lecler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital delay device, digital oscillator clock signal generator and...
- Publication number 20050104644
- Publication date May 19, 2005
- Luc Montperrus
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Device and method for forwarding a message
- Publication number 20050025169
- Publication date Feb 3, 2005
- Cesar Douady
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Jean-Jacques LECLER

Person

Patents Grantslast 30 patents

Dram-aware caching

Memory bank group interleaving

Dynamic memory scheduling routine with enhanced bank-group batching

Method and apparatus for ternary mapping

Zero-latency network on chip (NoC)

DMA engine with STLB prefetch capabilities and tethered prefetching

Three channel cache-coherency socket protocol

System translation look-aside buffer with request-based allocation...

Zero-latency network on chip (NoC)

Network on chip (NoC) with QoS features

Digital delay device, digital oscillator clock signal generator and...

Patents Applicationslast 30 patents

DRAM-AWARE CACHING

CONTROLLED EARLY RESPONSE IN MASTER-SLAVE SYSTEMS

SCHEDULING MEMORY TRANSACTIONS

MEMORY BANK GROUP INTERLEAVING

THREE CHANNEL CACHE-COHERENCY SOCKET PROTOCOL

ZERO-LATENCY NETWORK ON CHIP (NOC)

SYSTEM TRANSLATION LOOK-ASIDE BUFFER INTEGRATED IN AN INTERCONNECT

SYSTEM TRANSLATION LOOK-ASIDE BUFFER WITH REQUEST-BASED ALLOCATION...

DMA ENGINE WITH STLB PREFETCH CAPABILITIES AND TETHERED PREFETCHING

NETWORK ON CHIP (NOC) WITH QOS FEATURES

Memory Access Latency Metering

NETWORK ON CHIP (NOC) WITH QOS FEATURES

Zero-latency network on chip (NoC)

Digital delay device, digital oscillator clock signal generator and...

Device and method for forwarding a message