Jean-Marc DAVEAU

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Grenoble, FR

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Patents Grantslast 30 patents

Information Patent Grant
Method for managing the operation of a test mode of a logic compone...
- Patent number 10,386,414
- Issue date Aug 20, 2019
- STMicroelectronics (Crolles 2) SAS
- Jean-Marc Daveau
- G01 - MEASURING TESTING
Information Patent Grant
Method for managing the operation of a circuit with triple modular...
- Patent number 9,417,282
- Issue date Aug 16, 2016
- STMicroelectronics (Crolles 2) SAS
- Jean-Marc Daveau
- G01 - MEASURING TESTING
Information Patent Grant
Signal processor executing variable size instructions using paralle...
- Patent number 6,944,748
- Issue date Sep 13, 2005
- STMicroelectronics S.A.
- José Sanches
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and arrangements for automatic synthesis of systems-on-chip
- Patent number 6,477,691
- Issue date Nov 5, 2002
- International Business Machines Corporation
- Reinaldo A. Bergamashi/Rab
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR MANAGING THE OPERATION OF A TEST MODE OF A LOGIC COMPONE...
- Publication number 20170205461
- Publication date Jul 20, 2017
- STMicroelectronics (Grenoble 2) SAS
- Jean-Marc DAVEAU
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR MANAGING THE OPERATION OF A CIRCUIT WITH TRIPLE MODULAR...
- Publication number 20150377962
- Publication date Dec 31, 2015
- STMicroelectronics (Crolles 2) SAS
- Jean-Marc DAVEAU
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR ESTIMATING THE RELIABILITY OF AN ELECTRONIC CIRCUIT, COR...
- Publication number 20110246811
- Publication date Oct 6, 2011
- STMicroelectronics S.A.
- Josep Torras Flaquer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital signal processor with parallel architecture
- Publication number 20020116596
- Publication date Aug 22, 2002
- STMicroelectronics S.A.
- Jose Sanches
- G06 - COMPUTING CALCULATING COUNTING