Jean-Yee-Mei Yang

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Thin oxide dummy tiling as charge protection
- Patent number 7,977,218
- Issue date Jul 12, 2011
- Spansion LLC
- Cinti Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using implanted poly-1 to improve charging protection in dual-poly...
- Patent number 7,553,727
- Issue date Jun 30, 2009
- Spansion LLC
- Ming-Sang Kwan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of formation of gate stack spacer and charge storage materia...
- Patent number 7,163,860
- Issue date Jan 16, 2007
- Spansion LLC
- Tazrien Kamal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Alignment marks with salicided spacers between bitlines for alignme...
- Patent number 7,098,546
- Issue date Aug 29, 2006
- FASL LLC
- Emmanuil H. Lingunis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory structure having tunable interlayer dielectric and method fo...
- Patent number 7,078,749
- Issue date Jul 18, 2006
- Spansion LLC
- Jean Yee-Mei Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming wordlines having irregular spacing in a memory a...
- Patent number 7,052,961
- Issue date May 30, 2006
- Spansion LLC
- Hidehiko Shiraiwa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Undoped oxide liner/BPSG for improved data retention
- Patent number 7,023,046
- Issue date Apr 4, 2006
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bitline implant utilizing dual poly
- Patent number 6,989,320
- Issue date Jan 24, 2006
- Advanced Micro Devices, Inc.
- Weidong Qian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device having silicided bitlines and method of forming the same
- Patent number 6,987,048
- Issue date Jan 17, 2006
- Advanced Micro Devices, Inc.
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-bit silicon nitride charge-trapping non-volatile memory cell
- Patent number 6,897,533
- Issue date May 24, 2005
- Advanced Micro Devices, Inc.
- Jean Yee-Mei Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and structure for protecting NROM devices from induced charg...
- Patent number 6,869,844
- Issue date Mar 22, 2005
- Advanced Micro Device, Inc.
- Zhizheng Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a planar structure charge trapping memory cel...
- Patent number 6,855,608
- Issue date Feb 15, 2005
- Advanced Micro Devices, Inc.
- Mark Ramsbey
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Dielectric extension to mitigate short channel effects
- Publication number 20080157199
- Publication date Jul 3, 2008
- Spansion LLC
- Vidyut Gopal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thin oxide dummy tiling as charge protection
- Publication number 20080153269
- Publication date Jun 26, 2008
- Cinti Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Using implanted poly-1 to improve charging protection in dual-poly...
- Publication number 20080150006
- Publication date Jun 26, 2008
- Spansion LLC
- Ming-Sang Kwan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE PROTECTION LAYER
- Publication number 20080135913
- Publication date Jun 12, 2008
- SPANSION LLC
- Rinji Sugino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bitline implant utilizing dual poly
- Publication number 20050255651
- Publication date Nov 17, 2005
- Weidong Qian
- H01 - BASIC ELECTRIC ELEMENTS

Jean-Yee-Mei Yang

Person

Patents Grantslast 30 patents

Thin oxide dummy tiling as charge protection

Using implanted poly-1 to improve charging protection in dual-poly...

Method of formation of gate stack spacer and charge storage materia...

Alignment marks with salicided spacers between bitlines for alignme...

Memory structure having tunable interlayer dielectric and method fo...

Method for forming wordlines having irregular spacing in a memory a...

Undoped oxide liner/BPSG for improved data retention

Bitline implant utilizing dual poly

Memory device having silicided bitlines and method of forming the same

Multi-bit silicon nitride charge-trapping non-volatile memory cell

Method and structure for protecting NROM devices from induced charg...

Method of fabricating a planar structure charge trapping memory cel...

Patents Applicationslast 30 patents

Dielectric extension to mitigate short channel effects

Thin oxide dummy tiling as charge protection

Using implanted poly-1 to improve charging protection in dual-poly...

MEMORY DEVICE PROTECTION LAYER

Bitline implant utilizing dual poly