Jeanne P. Bickford

Person

Essex Junction, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Product performance test binning
- Patent number 10,794,952
- Issue date Oct 6, 2020
- International Business Machines Corporation
- Jeanne Bickford
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit chip reliability qualification using a sample-sp...
- Patent number 10,539,611
- Issue date Jan 21, 2020
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Grant
Pre-test power-optimized bin reassignment following selective volta...
- Patent number 10,295,592
- Issue date May 21, 2019
- Global Foundries Inc.
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methodology to prevent metal lines from current pulse damage
- Patent number 10,216,870
- Issue date Feb 26, 2019
- International Business Machines Corporation
- Jeanne P. S. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for managing semiconductor manufacturing defects
- Patent number 10,089,161
- Issue date Oct 2, 2018
- International Business Machines Corporation
- Jeanne P. S. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Product performance test binning
- Patent number 10,067,184
- Issue date Sep 4, 2018
- International Business Machines Corporation
- Theodoros Anemikos
- G01 - MEASURING TESTING
Information Patent Grant
Performance matching in three-dimensional (3D) integrated circuit (...
- Patent number 10,013,519
- Issue date Jul 3, 2018
- GLOBALFOUNDRIES Inc.
- Sudeep Mandal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Burn-in power performance optimization
- Patent number 9,940,430
- Issue date Apr 10, 2018
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit chip reliability qualification using a sample-sp...
- Patent number 9,891,275
- Issue date Feb 13, 2018
- International Business Machines Corporation
- Jeanne P. Bickford
- G05 - CONTROLLING REGULATING
Information Patent Grant
System and method for managing semiconductor manufacturing defects
- Patent number 9,880,892
- Issue date Jan 30, 2018
- International Business Machines Corporation
- Jeanne P. S. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing/power risk optimized selective voltage binning using non-lin...
- Patent number 9,865,486
- Issue date Jan 9, 2018
- GLOBALFOUNDRIES Inc.
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area and/or power optimization through post-layout modification of...
- Patent number 9,852,259
- Issue date Dec 26, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip usable life depletion meter and associated method
- Patent number 9,791,502
- Issue date Oct 17, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G11 - INFORMATION STORAGE
Information Patent Grant
Selective voltage binning leakage screen
- Patent number 9,772,374
- Issue date Sep 26, 2017
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Grant
Temperature-aware integrated circuit design methods and systems
- Patent number 9,767,240
- Issue date Sep 19, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pre-test power-optimized bin reassignment following selective volta...
- Patent number 9,759,767
- Issue date Sep 12, 2017
- GLOBALFOUNDRIES Inc.
- Igor Arsovski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electromigration-aware integrated circuit design methods and systems
- Patent number 9,740,815
- Issue date Aug 22, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Threshold voltage (VT)-type transistor sensitive and/or fan-out sen...
- Patent number 9,653,330
- Issue date May 16, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit chip reliability using reliability-optimized fai...
- Patent number 9,639,645
- Issue date May 2, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for identifying operating temperatures and modify...
- Patent number 9,625,325
- Issue date Apr 18, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods to prevent incorporation of a used integrated c...
- Patent number 9,618,566
- Issue date Apr 11, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit chip design methods and systems using process wi...
- Patent number 9,619,609
- Issue date Apr 11, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for timing violations in a circuit
- Patent number 9,569,571
- Issue date Feb 14, 2017
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and structure for multi-core chip product test and selective...
- Patent number 9,557,378
- Issue date Jan 31, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for controlling integrated circuit chip tempera...
- Patent number 9,552,447
- Issue date Jan 24, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple manufacturing line qualification
- Patent number 9,536,796
- Issue date Jan 3, 2017
- Globalfoundries Inc.
- Jeanne P. Bickford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for semiconductor line scribe line centering
- Patent number 9,514,999
- Issue date Dec 6, 2016
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reliability-optimized selective voltage binning
- Patent number 9,489,482
- Issue date Nov 8, 2016
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reliability test screen optimization
- Patent number 9,429,619
- Issue date Aug 30, 2016
- GLOBALFOUNDRIES Inc.
- Theodoros E. Anemikos
- G05 - CONTROLLING REGULATING
Information Patent Grant
System integrator and system integration method with reliability op...
- Patent number 9,354,953
- Issue date May 31, 2016
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PRODUCT PERFORMANCE TEST BINNING
- Publication number 20180292456
- Publication date Oct 11, 2018
- International Business Machines Corporation
- Jeanne Bickford
- G01 - MEASURING TESTING
Information Patent Application
SLEW WINDOW SHIFT PLACEMENT METHOD TO REDUCE HOT SPOTS AND RECOVER...
- Publication number 20180089354
- Publication date Mar 29, 2018
- GLOBALFOUNDRIES INC.
- Alok Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMANCE MATCHING IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (...
- Publication number 20180082007
- Publication date Mar 22, 2018
- GLOBALFOUNDRIES INC.
- Sudeep Mandal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR MANAGING SEMICONDUCTOR MANUFACTURING DEFECTS
- Publication number 20180074874
- Publication date Mar 15, 2018
- International Business Machines Corporation
- Jeanne P. S. Bickford
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT CHIP RELIABILITY QUALIFICATION USING A SAMPLE-SP...
- Publication number 20180052201
- Publication date Feb 22, 2018
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
TIMING/POWER RISK OPTIMIZED SELECTIVE VOLTAGE BINNING USING NON-LIN...
- Publication number 20170287756
- Publication date Oct 5, 2017
- GLOBALFOUNDRIES INC.
- IGOR ARSOVSKI
- G01 - MEASURING TESTING
Information Patent Application
PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTA...
- Publication number 20170276726
- Publication date Sep 28, 2017
- GLOBALFOUNDRIES INC.
- Igor Arsovski
- G01 - MEASURING TESTING
Information Patent Application
AREA AND/OR POWER OPTIMIZATION THROUGH POST-LAYOUT MODIFICATION OF...
- Publication number 20170212977
- Publication date Jul 27, 2017
- GLOBALFOUNDRIES INC.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESISTANCE MEASUREMENT-DEPENDENT INTEGRATED CIRCUIT CHIP RELIABILIT...
- Publication number 20170212165
- Publication date Jul 27, 2017
- GLOBALFOUNDRIES INC.
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
METHODOLOGY TO PREVENT METAL LINES FROM CURRENT PULSE DAMAGE
- Publication number 20170199949
- Publication date Jul 13, 2017
- International Business Machines Corporation
- JEANNE P. S. BICKFORD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BURN-IN POWER PERFORMANCE OPTIMIZATION
- Publication number 20170161426
- Publication date Jun 8, 2017
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEMPERATURE-AWARE INTEGRATED CIRCUIT DESIGN METHODS AND SYSTEMS
- Publication number 20170147727
- Publication date May 25, 2017
- GLOBALFOUNDRIES INC.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTROMIGRATION-AWARE INTEGRATED CIRCUIT DESIGN METHODS AND SYSTEMS
- Publication number 20170116367
- Publication date Apr 27, 2017
- GolbalFoundries Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT CHIP DESIGN METHODS AND SYSTEMS USING PROCESS WI...
- Publication number 20170083661
- Publication date Mar 23, 2017
- GLOBALFOUNDRIES INC.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT CHIP RELIABILITY QUALIFICATION USING A SAMPLE-SP...
- Publication number 20160377674
- Publication date Dec 29, 2016
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT CHIP RELIABILITY USING RELIABILITY-OPTIMIZED FAI...
- Publication number 20160371413
- Publication date Dec 22, 2016
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-CHIP USABLE LIFE DEPLETION METER AND ASSOCIATED METHOD
- Publication number 20160320214
- Publication date Nov 3, 2016
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTA...
- Publication number 20160313394
- Publication date Oct 27, 2016
- International Business Machines Corporation
- Igor Arsovski
- G01 - MEASURING TESTING
Information Patent Application
SYSTEMS AND METHODS FOR CONTROLLING INTEGRATED CIRCUIT CHIP TEMPERA...
- Publication number 20160314229
- Publication date Oct 27, 2016
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS TO PREVENT INCORPORATION OF A USED INTEGRATED C...
- Publication number 20160238653
- Publication date Aug 18, 2016
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR IDENTIFYING OPERATING TEMPERATURES AND MODIFY...
- Publication number 20160240479
- Publication date Aug 18, 2016
- GLOBALFOUNDRIES INC.
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM INTEGRATOR AND SYSTEM INTEGRATION METHOD WITH RELIABILITY OP...
- Publication number 20160026517
- Publication date Jan 28, 2016
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UPDATING RELIABILITY PREDICTIONS USING MANUFACTURING ASSESSMENT DATA
- Publication number 20160019328
- Publication date Jan 21, 2016
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LIMITING SKEW BETWEEN DIFFERENT DEVICE TYPES TO MEET PERFORMANCE RE...
- Publication number 20150242560
- Publication date Aug 27, 2015
- International Business Machines Corporation
- Igor ARSOVSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR MANAGING SEMICONDUCTOR MANUFACTURING DEFECTS
- Publication number 20150241511
- Publication date Aug 27, 2015
- International Business Machines Corporation
- Jeanne P.S. Bickford
- G01 - MEASURING TESTING
Information Patent Application
BALANCING SENSITIVITIES WITH RESPECT TO TIMING CLOSURE FOR INTEGRAT...
- Publication number 20150234969
- Publication date Aug 20, 2015
- International Business Machines Corporation
- Jeanne P. BICKFORD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE RELIABILITY MODEL AND METHODOLOGIES FOR USE TH...
- Publication number 20150106780
- Publication date Apr 16, 2015
- International Business Machines Corporation
- Jeanne P. BICKFORD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINING INTRA-DIE VARIATION OF AN INTEGRATED CIRCUIT
- Publication number 20150048860
- Publication date Feb 19, 2015
- International Business Machines Corporation
- Jeanne P.S. Bickford
- G01 - MEASURING TESTING
Information Patent Application
IN-SITU COMPUTING SYSTEM FAILURE AVOIDANCE
- Publication number 20150033081
- Publication date Jan 29, 2015
- International Business Machines Corporation
- Jeanne P.S. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR SINGLE CELL PRODUCT PATH DELAY ANALYSIS
- Publication number 20150033199
- Publication date Jan 29, 2015
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING

Jeanne P. Bickford

Person

Patents Grantslast 30 patents

Product performance test binning

Integrated circuit chip reliability qualification using a sample-sp...

Pre-test power-optimized bin reassignment following selective volta...

Methodology to prevent metal lines from current pulse damage

System and method for managing semiconductor manufacturing defects

Product performance test binning

Performance matching in three-dimensional (3D) integrated circuit (...

Burn-in power performance optimization

Integrated circuit chip reliability qualification using a sample-sp...

System and method for managing semiconductor manufacturing defects

Timing/power risk optimized selective voltage binning using non-lin...

Area and/or power optimization through post-layout modification of...

On-chip usable life depletion meter and associated method

Selective voltage binning leakage screen

Temperature-aware integrated circuit design methods and systems

Pre-test power-optimized bin reassignment following selective volta...

Electromigration-aware integrated circuit design methods and systems

Threshold voltage (VT)-type transistor sensitive and/or fan-out sen...

Integrated circuit chip reliability using reliability-optimized fai...

System and method for identifying operating temperatures and modify...

Systems and methods to prevent incorporation of a used integrated c...

Integrated circuit chip design methods and systems using process wi...

Method and system for timing violations in a circuit

Method and structure for multi-core chip product test and selective...

Systems and methods for controlling integrated circuit chip tempera...

Multiple manufacturing line qualification

Systems and methods for semiconductor line scribe line centering

Reliability-optimized selective voltage binning

Reliability test screen optimization

System integrator and system integration method with reliability op...

Patents Applicationslast 30 patents

PRODUCT PERFORMANCE TEST BINNING

SLEW WINDOW SHIFT PLACEMENT METHOD TO REDUCE HOT SPOTS AND RECOVER...

PERFORMANCE MATCHING IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (...

SYSTEM AND METHOD FOR MANAGING SEMICONDUCTOR MANUFACTURING DEFECTS

INTEGRATED CIRCUIT CHIP RELIABILITY QUALIFICATION USING A SAMPLE-SP...

TIMING/POWER RISK OPTIMIZED SELECTIVE VOLTAGE BINNING USING NON-LIN...

PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTA...

AREA AND/OR POWER OPTIMIZATION THROUGH POST-LAYOUT MODIFICATION OF...

RESISTANCE MEASUREMENT-DEPENDENT INTEGRATED CIRCUIT CHIP RELIABILIT...

METHODOLOGY TO PREVENT METAL LINES FROM CURRENT PULSE DAMAGE

BURN-IN POWER PERFORMANCE OPTIMIZATION

TEMPERATURE-AWARE INTEGRATED CIRCUIT DESIGN METHODS AND SYSTEMS

ELECTROMIGRATION-AWARE INTEGRATED CIRCUIT DESIGN METHODS AND SYSTEMS

INTEGRATED CIRCUIT CHIP DESIGN METHODS AND SYSTEMS USING PROCESS WI...

INTEGRATED CIRCUIT CHIP RELIABILITY QUALIFICATION USING A SAMPLE-SP...

INTEGRATED CIRCUIT CHIP RELIABILITY USING RELIABILITY-OPTIMIZED FAI...

ON-CHIP USABLE LIFE DEPLETION METER AND ASSOCIATED METHOD

PRE-TEST POWER-OPTIMIZED BIN REASSIGNMENT FOLLOWING SELECTIVE VOLTA...

SYSTEMS AND METHODS FOR CONTROLLING INTEGRATED CIRCUIT CHIP TEMPERA...

SYSTEMS AND METHODS TO PREVENT INCORPORATION OF A USED INTEGRATED C...

SYSTEM AND METHOD FOR IDENTIFYING OPERATING TEMPERATURES AND MODIFY...

SYSTEM INTEGRATOR AND SYSTEM INTEGRATION METHOD WITH RELIABILITY OP...

UPDATING RELIABILITY PREDICTIONS USING MANUFACTURING ASSESSMENT DATA

LIMITING SKEW BETWEEN DIFFERENT DEVICE TYPES TO MEET PERFORMANCE RE...

SYSTEM AND METHOD FOR MANAGING SEMICONDUCTOR MANUFACTURING DEFECTS

BALANCING SENSITIVITIES WITH RESPECT TO TIMING CLOSURE FOR INTEGRAT...

SEMICONDUCTOR DEVICE RELIABILITY MODEL AND METHODOLOGIES FOR USE TH...

DETERMINING INTRA-DIE VARIATION OF AN INTEGRATED CIRCUIT

IN-SITU COMPUTING SYSTEM FAILURE AVOIDANCE

SYSTEMS AND METHODS FOR SINGLE CELL PRODUCT PATH DELAY ANALYSIS