Jeen Miin

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multiple multi-threaded processors having an L1 instruction cache a...
- Patent number 8,087,024
- Issue date Dec 27, 2011
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Scalable, high-performance, global interconnect scheme for multi-th...
- Patent number 7,707,266
- Issue date Apr 27, 2010
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread-based engine cache partitioning
- Patent number 7,536,692
- Issue date May 19, 2009
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined tag and data ECC for enhanced soft error recovery from cac...
- Patent number 7,376,877
- Issue date May 20, 2008
- Intel Corporation
- Nhon Toai Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to handle parity errors in flow control channels
- Patent number 7,337,371
- Issue date Feb 26, 2008
- Intel Corporation
- Chen-Chi Kuo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Processing element with next and previous neighbor registers for di...
- Patent number 7,275,145
- Issue date Sep 25, 2007
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using hardware or firmware for cache tag and data ECC soft error co...
- Patent number 6,802,039
- Issue date Oct 5, 2004
- Intel Corporation
- Nhon Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined tag and data ECC for enhanced soft error recovery from cac...
- Patent number 6,772,383
- Issue date Aug 3, 2004
- Intel Corporation
- Nhon Toai Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for live-lock prevention
- Patent number 6,574,689
- Issue date Jun 3, 2003
- Intel Corporation
- Nazar A. Zaidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for processing cache misses
- Patent number 6,438,650
- Issue date Aug 20, 2002
- Intel Corporation
- Nhon T. Quach
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Multiple multi-threaded processors having an L1 instruction cache a...
- Publication number 20090089546
- Publication date Apr 2, 2009
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable, high-performance, global interconnect scheme for multi-th...
- Publication number 20060112206
- Publication date May 25, 2006
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing element with next and previous neighbor registers
- Publication number 20050149691
- Publication date Jul 7, 2005
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to handle parity errors in flow control channels
- Publication number 20050141535
- Publication date Jun 30, 2005
- Chen-Chi Kuo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Servicing engine cache requests
- Publication number 20050108479
- Publication date May 19, 2005
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Thread-based engine cache partitioning
- Publication number 20050102486
- Publication date May 12, 2005
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamically caching engine instructions
- Publication number 20050102474
- Publication date May 12, 2005
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Executing instructions on a processor
- Publication number 20050050306
- Publication date Mar 3, 2005
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and process for scheduling data packet collection
- Publication number 20040252687
- Publication date Dec 16, 2004
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Combined tag and data ECC for enhanced soft error recovery from cac...
- Publication number 20040199851
- Publication date Oct 7, 2004
- Nhon Toai Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Network processor performance monitoring system and method
- Publication number 20040006724
- Publication date Jan 8, 2004
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Multiple multi-threaded processors having an L1 instruction cache a...

Scalable, high-performance, global interconnect scheme for multi-th...

Thread-based engine cache partitioning

Combined tag and data ECC for enhanced soft error recovery from cac...

Method and apparatus to handle parity errors in flow control channels

Processing element with next and previous neighbor registers for di...

Using hardware or firmware for cache tag and data ECC soft error co...

Combined tag and data ECC for enhanced soft error recovery from cac...

Method and apparatus for live-lock prevention

Method and apparatus for processing cache misses

Patents Applicationslast 30 patents

Multiple multi-threaded processors having an L1 instruction cache a...

Scalable, high-performance, global interconnect scheme for multi-th...

Processing element with next and previous neighbor registers

Method and apparatus to handle parity errors in flow control channels

Servicing engine cache requests

Thread-based engine cache partitioning

Dynamically caching engine instructions

Executing instructions on a processor

Method and process for scheduling data packet collection

Combined tag and data ECC for enhanced soft error recovery from cac...

Network processor performance monitoring system and method