Jeesung Jung

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
LDMOS device with a field plate contact metal layer with a sub-maxi...
- Patent number 10,665,712
- Issue date May 26, 2020
- Monolithic Power Systems, Inc.
- Eric Braun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating LDMOS with self-aligned body
- Patent number 10,090,409
- Issue date Oct 2, 2018
- Monolithic Power Systems, Inc.
- Joel M. McGregor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing method of selectively etched DMOS body pickup
- Patent number 9,893,170
- Issue date Feb 13, 2018
- Monolithic Power Systems, Inc.
- Ji-Hyoung Yoo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lateral DMOS and the method for forming thereof
- Patent number 9,893,146
- Issue date Feb 13, 2018
- Monolithic Power Systems, Inc.
- Eric Braun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating low-cost isolated resurf LDMOS and associate...
- Patent number 9,502,251
- Issue date Nov 22, 2016
- Monolithic Power Systems, Inc.
- Joel M. McGregor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDMOS device with short channel and associated fabrication method
- Patent number 9,087,774
- Issue date Jul 21, 2015
- Monolithic Power Systems, Inc.
- Jeesung Jung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming dual gate insulation layers and semiconductor de...
- Patent number 8,916,439
- Issue date Dec 23, 2014
- Monolithic Power Systems, Inc.
- Ji-Hyoung Yoo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of manufacturing lateral diffused MOS devices with layout c...
- Patent number 8,796,100
- Issue date Aug 5, 2014
- Monolithic Power Systems, Inc.
- Jeesung Jung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
U-shape RESURF MOSFET devices and associated methods of manufacturing
- Patent number 8,748,980
- Issue date Jun 10, 2014
- Monolithic Power Systems, Inc.
- Jeesung Jung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bipolar junction transistor with layout controlled base and associa...
- Patent number 8,581,365
- Issue date Nov 12, 2013
- Monolithic Power Systems, Inc.
- Jeesung Jung
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
LATERAL TRANSISTOR WITH LATERAL CONDUCTIVE FIELD PLATE OVER A FIELD...
- Publication number 20210193805
- Publication date Jun 24, 2021
- Monolithic Power Systems, Inc.
- Ji-Hyoung Yoo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LDMOS DEVICE WITH A DRAIN CONTACT STRUCTURE WITH REDUCED SIZE
- Publication number 20200144381
- Publication date May 7, 2020
- Monolithic Power Systems, Inc.
- Eric Braun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LDMOS DEVICE WITH A FIELD PLATE CONTACT METAL LAYER WITH A SUB-MAXI...
- Publication number 20200075760
- Publication date Mar 5, 2020
- Monolithic Power Systems Co., Ltd.
- Eric Braun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING LDMOS WITH SELF-ALIGNED BODY
- Publication number 20180374949
- Publication date Dec 27, 2018
- Monolithic Power Systems, Inc.
- Joel M. McGregor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING LDMOS WITH SELF-ALIGNED BODY
- Publication number 20180090613
- Publication date Mar 29, 2018
- Monolithic Power Systems, Inc.
- Joel M. McGregor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LDMOS DEVICE WITH IMPROVED AVALANCHE ENERGY AND ASSOCIATED FABRICAT...
- Publication number 20150162441
- Publication date Jun 11, 2015
- Joel M. McGregor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LDMOS DEVICE WITH SHORT CHANNEL AND ASSOCIATED FABRICATION METHOD
- Publication number 20150084126
- Publication date Mar 26, 2015
- Monolithic Power Systems, Inc.
- Jeesung Jung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LDMOS DEVICE WITH IMPROVED AVALANCHE ENERGY AND ASSOCIATED FABRICAT...
- Publication number 20150001620
- Publication date Jan 1, 2015
- Monolithic Power Systems, Inc.
- Joel M. McGregor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING DUAL GATE INSULATION LAYERS AND SEMICONDUCTOR DE...
- Publication number 20140024186
- Publication date Jan 23, 2014
- Monolithic Power Systems, Inc.
- Ji-Hyoung Yoo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
U-SHAPE RESURF MOSFET DEVICES AND ASSOCIATED METHODS OF MANUFACTURING
- Publication number 20130049113
- Publication date Feb 28, 2013
- Jeesung Jung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF MANUFACTURING LATERAL DIFFUSED MOS DEVICES WITH LAYOUT C...
- Publication number 20130040432
- Publication date Feb 14, 2013
- Jeesung Jung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIPOLAR JUNCTION TRANSISTOR WITH LAYOUT CONTROLLED BASE AND ASSOCIA...
- Publication number 20120267764
- Publication date Oct 25, 2012
- Jeesung Jung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES WITH LAYOUT CONTROLLED CHANNEL AND ASSOCIATED...
- Publication number 20120244668
- Publication date Sep 27, 2012
- Jeesung Jung
- H01 - BASIC ELECTRIC ELEMENTS

Jeesung Jung

Person

Patents Grantslast 30 patents

LDMOS device with a field plate contact metal layer with a sub-maxi...

Method for fabricating LDMOS with self-aligned body

Manufacturing method of selectively etched DMOS body pickup

Lateral DMOS and the method for forming thereof

Method for fabricating low-cost isolated resurf LDMOS and associate...

LDMOS device with short channel and associated fabrication method

Method for forming dual gate insulation layers and semiconductor de...

Methods of manufacturing lateral diffused MOS devices with layout c...

U-shape RESURF MOSFET devices and associated methods of manufacturing

Bipolar junction transistor with layout controlled base and associa...

Patents Applicationslast 30 patents

LATERAL TRANSISTOR WITH LATERAL CONDUCTIVE FIELD PLATE OVER A FIELD...

LDMOS DEVICE WITH A DRAIN CONTACT STRUCTURE WITH REDUCED SIZE

LDMOS DEVICE WITH A FIELD PLATE CONTACT METAL LAYER WITH A SUB-MAXI...

METHOD FOR FABRICATING LDMOS WITH SELF-ALIGNED BODY

METHOD FOR FABRICATING LDMOS WITH SELF-ALIGNED BODY

LDMOS DEVICE WITH IMPROVED AVALANCHE ENERGY AND ASSOCIATED FABRICAT...

LDMOS DEVICE WITH SHORT CHANNEL AND ASSOCIATED FABRICATION METHOD

LDMOS DEVICE WITH IMPROVED AVALANCHE ENERGY AND ASSOCIATED FABRICAT...

METHOD FOR FORMING DUAL GATE INSULATION LAYERS AND SEMICONDUCTOR DE...

U-SHAPE RESURF MOSFET DEVICES AND ASSOCIATED METHODS OF MANUFACTURING

METHODS OF MANUFACTURING LATERAL DIFFUSED MOS DEVICES WITH LAYOUT C...

BIPOLAR JUNCTION TRANSISTOR WITH LAYOUT CONTROLLED BASE AND ASSOCIA...

SEMICONDUCTOR DEVICES WITH LAYOUT CONTROLLED CHANNEL AND ASSOCIATED...