JEFF L. WARNER

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AUSTIN, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit with power saving feature
- Patent number 9,806,019
- Issue date Oct 31, 2017
- NXP USA, INC.
- Anis M. Jarrar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Active tiling placement for improved latch-up immunity
- Patent number 8,765,607
- Issue date Jul 1, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Robert S. Ruth
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT WITH POWER SAVING FEATURE
- Publication number 20170084535
- Publication date Mar 23, 2017
- FREESCALE SEMICONDUCTOR, INC.
- ANIS M. JARRAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Active Tiling Placement for Improved Latch-up Immunity
- Publication number 20140264728
- Publication date Sep 18, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Robert S. Ruth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Active Tiling Placement for Improved Latch-Up Immunity
- Publication number 20120306045
- Publication date Dec 6, 2012
- Robert S. Ruth
- H01 - BASIC ELECTRIC ELEMENTS