Jeff Rearick

Person

Court Ft Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Devices, systems, and methods for detecting and mitigating silent d...
- Patent number 11,966,283
- Issue date Apr 23, 2024
- Advanced Micro Devices, Inc.
- Divya Madapusi Srinivas Prasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for an embedded time domain reflectometry test
- Patent number 7,640,468
- Issue date Dec 29, 2009
- Agilent Technologies, Inc.
- David L. Linam
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and method for compensating clock period elongation durin...
- Patent number 7,580,806
- Issue date Aug 25, 2009
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Richard S. Rodgers
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for enabling a user to determine whether a def...
- Patent number 7,519,875
- Issue date Apr 14, 2009
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Jeffrey R. Rearick
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for comparing circuit performance between functi...
- Patent number 7,516,379
- Issue date Apr 7, 2009
- Avago Technologies General IP (Singapore) Pte. Ltd.
- John G. Rohrbaugh
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for reconfiguring scan chains
- Patent number 7,502,978
- Issue date Mar 10, 2009
- Avago Technologies General IP (Singapore) Pte. Ltd.
- John Bratt
- G01 - MEASURING TESTING
Information Patent Grant
Testing target resistances in circuit assemblies
- Patent number 7,411,407
- Issue date Aug 12, 2008
- Agilent Technologies, Inc.
- Jeffrey R. Rearick
- G01 - MEASURING TESTING
Information Patent Grant
Programmable hysteresis for boundary-scan testing
- Patent number 7,222,278
- Issue date May 22, 2007
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Charles E. Moore
- G01 - MEASURING TESTING
Information Patent Grant
System and method for automatic masking of compressed scan chains w...
- Patent number 7,143,324
- Issue date Nov 28, 2006
- Avago Technologies General IP (Singapore) Pte. Ltd.
- John T. Bratt
- G01 - MEASURING TESTING
Information Patent Grant
Method for determining the impact on test coverage of scan chain pa...
- Patent number 7,139,948
- Issue date Nov 21, 2006
- Avago Technologies General IP(Singapore) Pte. Ltd.
- Jeffrey R. Rearick
- G01 - MEASURING TESTING
Information Patent Grant
Hierarchically-controlled automatic test pattern generation
- Patent number 7,139,955
- Issue date Nov 21, 2006
- Avago Technologies General IP (Singapore) Pte. Ltd.
- John G Rohrbaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for compensating clock period elongation durin...
- Patent number 7,079,973
- Issue date Jul 18, 2006
- Avago Technologies General IP Pte. Ltd.
- Richard S. Rodgers
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for facilitating testing of pads of integrated...
- Patent number 7,043,674
- Issue date May 9, 2006
- Jeffrey R. Rearick
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for deriving a bounded set of path delay test...
- Patent number 7,039,845
- Issue date May 2, 2006
- Jeff Rearick
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for facilitating testing of pad drivers of inte...
- Patent number 6,986,085
- Issue date Jan 10, 2006
- Agilent Technologies, Inc.
- Jeffrey R. Rearick
- G01 - MEASURING TESTING
Information Patent Grant
System and method for evaluating an integrated circuit design
- Patent number 6,944,837
- Issue date Sep 13, 2005
- Agilent Technologies, Inc.
- John G Rohrbaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for facilitating testing of pad receivers of in...
- Patent number 6,907,376
- Issue date Jun 14, 2005
- Agilent Technologies, Inc.
- Shad R. Shepston
- G01 - MEASURING TESTING
Information Patent Grant
Partitioning integrated circuit hierarchy
- Patent number 6,895,562
- Issue date May 17, 2005
- Agilent Technologies, Inc.
- John G Rohrbaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for generating a set of test vectors using non...
- Patent number 6,865,706
- Issue date Mar 8, 2005
- Agilent Technologies, Inc.
- John G Rohrbaugh
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for testing receiver terminations in integrated...
- Patent number 6,859,059
- Issue date Feb 22, 2005
- Agilent Technologies, Inc.
- John G. Rohrbaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for facilitating driver strength testing of int...
- Patent number 6,762,614
- Issue date Jul 13, 2004
- Agilent Technologies, Inc.
- Jeffrey R. Rearick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus of boundary scan testing for AC-coupled differ...
- Patent number 6,763,486
- Issue date Jul 13, 2004
- Agilent Technologies, Inc.
- Benny W H Lai
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for facilitating automated test equipment funct...
- Patent number 6,741,946
- Issue date May 25, 2004
- Agilent Technologies, Inc.
- John G. Rohrbaugh
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing current sinking/sourcing capabilit...
- Patent number 6,737,858
- Issue date May 18, 2004
- Agilent Technologies, Inc.
- Jeff Rearick
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for facilitating testing of pad drivers of inte...
- Patent number 6,721,920
- Issue date Apr 13, 2004
- Agilent Technologies, Inc.
- Jeff Rearick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for reducing stored patterns for IC test by embedding built-...
- Patent number 6,715,105
- Issue date Mar 30, 2004
- Agilent Technologies, Inc.
- Jeff Rearick
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for measuring the quality of delay test patterns
- Patent number 6,708,139
- Issue date Mar 16, 2004
- Agilent Technologies, Inc.
- Jeff Rearick
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for testing integrated circuits
- Patent number 6,707,313
- Issue date Mar 16, 2004
- Agilent Technologies, Inc.
- John G Rohrbaugh
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for facilitating testing of pad receivers of in...
- Patent number 6,658,613
- Issue date Dec 2, 2003
- Agilent Technologies, Inc.
- Jeffrey R. Rearick
- G01 - MEASURING TESTING
Information Patent Grant
SERDES cooperates with the boundary scan test technique
- Patent number 6,653,957
- Issue date Nov 25, 2003
- Agilent Technologies, Inc.
- Sylvia Patterson
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DEVICES, SYSTEMS, AND METHODS FOR DETECTING AND MITIGATING SILENT D...
- Publication number 20240264900
- Publication date Aug 8, 2024
- ADVANCED MICRO DEVICES, INC.
- Divya Madapusi Srinivas Prasad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Testing target resistances in circuit assemblies
- Publication number 20070143047
- Publication date Jun 21, 2007
- Jeffrey R. Rearick
- G01 - MEASURING TESTING
Information Patent Application
Apparatus and method for compensating clock period elongation durin...
- Publication number 20060167645
- Publication date Jul 27, 2006
- Richard S. Rogers
- G01 - MEASURING TESTING
Information Patent Application
Systems and methods for facilitating testing of integrated circuits
- Publication number 20060156139
- Publication date Jul 13, 2006
- John Rohrbaugh
- G01 - MEASURING TESTING
Information Patent Application
Systems and methods for designing integrated circuits
- Publication number 20060150136
- Publication date Jul 6, 2006
- John Bratt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and methods for reconfiguring scan chains
- Publication number 20060150040
- Publication date Jul 6, 2006
- John Bratt
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for an embedded time domain reflectometry test
- Publication number 20060123305
- Publication date Jun 8, 2006
- David L. Linam
- G01 - MEASURING TESTING
Information Patent Application
System and method for automatic masking of compressed scan chains w...
- Publication number 20060095818
- Publication date May 4, 2006
- John T. Bratt
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for enabling a user to determine whether a def...
- Publication number 20060039211
- Publication date Feb 23, 2006
- Jeffrey R. Rearick
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit and method for comparing circuit performance between functi...
- Publication number 20050229056
- Publication date Oct 13, 2005
- John G. Rohrbaugh
- G01 - MEASURING TESTING
Information Patent Application
Apparatus and method for compensating clock period elongation durin...
- Publication number 20050222795
- Publication date Oct 6, 2005
- Richard S. Rodgers
- G01 - MEASURING TESTING
Information Patent Application
Programmable hysteresis for boundary-scan testing
- Publication number 20050060624
- Publication date Mar 17, 2005
- Charles E. Moore
- G01 - MEASURING TESTING
Information Patent Application
Method for determining the impact on test coverage of scan chain pa...
- Publication number 20040204895
- Publication date Oct 14, 2004
- Jeffrey R. Rearick
- G01 - MEASURING TESTING
Information Patent Application
Generating test patterns for testing an integrated circuit
- Publication number 20040187060
- Publication date Sep 23, 2004
- John G. Rohrbaugh
- G01 - MEASURING TESTING
Information Patent Application
Hierarchically-controlled automatic test pattern generation
- Publication number 20040153928
- Publication date Aug 5, 2004
- John G. Rohrbaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and methods for testing receiver terminations in integrated...
- Publication number 20040130344
- Publication date Jul 8, 2004
- John G. Rohrbaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and methods for testing tri-state bus drivers
- Publication number 20040123194
- Publication date Jun 24, 2004
- John G. Rohrbaugh
- G01 - MEASURING TESTING
Information Patent Application
Systems and methods for testing tri-state bus drivers
- Publication number 20040123195
- Publication date Jun 24, 2004
- John G. Rohrbaugh
- G01 - MEASURING TESTING
Information Patent Application
System and method for evaluating an integrated circuit design
- Publication number 20040123206
- Publication date Jun 24, 2004
- John G. Rohrbaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Partitioning integrated circuit hierarchy
- Publication number 20040044972
- Publication date Mar 4, 2004
- John G. Rohrbaugh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and methods for facilitating testing of pads of integrated...
- Publication number 20040044936
- Publication date Mar 4, 2004
- Jeffrey R. Rearick
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for measuring the quality of delay test patterns
- Publication number 20030204350
- Publication date Oct 30, 2003
- Jeff Rearick
- G01 - MEASURING TESTING
Information Patent Application
Systems and methods for facilitating driver strength testing of int...
- Publication number 20030197520
- Publication date Oct 23, 2003
- Jeffrey R. Rearick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for deriving a bounded set of path delay test...
- Publication number 20030188246
- Publication date Oct 2, 2003
- Jeff Rearick
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for testing current sinking/sourcing capabilit...
- Publication number 20030173989
- Publication date Sep 18, 2003
- Jeff Rearick
- G01 - MEASURING TESTING
Information Patent Application
Systems and methods for facilitating testing of pad drivers of inte...
- Publication number 20030172332
- Publication date Sep 11, 2003
- Jeffrey R. Rearick
- G01 - MEASURING TESTING
Information Patent Application
Systems and methods for facilitating testing of pad receivers of in...
- Publication number 20030158691
- Publication date Aug 21, 2003
- Shad R. Shepston
- G01 - MEASURING TESTING
Information Patent Application
Systems and methods for facilitating automated test equipment funct...
- Publication number 20030158690
- Publication date Aug 21, 2003
- John G. Rohrbaugh
- G01 - MEASURING TESTING
Information Patent Application
Systems and methods for facilitating testing of pad drivers of inte...
- Publication number 20020188901
- Publication date Dec 12, 2002
- Jeff Rearick
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus of boundary scan testing for AC-coupled differ...
- Publication number 20020170011
- Publication date Nov 14, 2002
- Benny W. H. Lai
- G01 - MEASURING TESTING

Jeff Rearick

Person

Patents Grantslast 30 patents

Devices, systems, and methods for detecting and mitigating silent d...

Method and apparatus for an embedded time domain reflectometry test

Apparatus and method for compensating clock period elongation durin...

Method and apparatus for enabling a user to determine whether a def...

Circuit and method for comparing circuit performance between functi...

Systems and methods for reconfiguring scan chains

Testing target resistances in circuit assemblies

Programmable hysteresis for boundary-scan testing

System and method for automatic masking of compressed scan chains w...

Method for determining the impact on test coverage of scan chain pa...

Hierarchically-controlled automatic test pattern generation

Apparatus and method for compensating clock period elongation durin...

Systems and methods for facilitating testing of pads of integrated...

Method and apparatus for deriving a bounded set of path delay test...

Systems and methods for facilitating testing of pad drivers of inte...

System and method for evaluating an integrated circuit design

Systems and methods for facilitating testing of pad receivers of in...

Partitioning integrated circuit hierarchy

Apparatus and method for generating a set of test vectors using non...

Systems and methods for testing receiver terminations in integrated...

Systems and methods for facilitating driver strength testing of int...

Method and apparatus of boundary scan testing for AC-coupled differ...

Systems and methods for facilitating automated test equipment funct...

Method and apparatus for testing current sinking/sourcing capabilit...

Systems and methods for facilitating testing of pad drivers of inte...

Method for reducing stored patterns for IC test by embedding built-...

Method and apparatus for measuring the quality of delay test patterns

Systems and methods for testing integrated circuits

Systems and methods for facilitating testing of pad receivers of in...

SERDES cooperates with the boundary scan test technique

Patents Applicationslast 30 patents

DEVICES, SYSTEMS, AND METHODS FOR DETECTING AND MITIGATING SILENT D...

Testing target resistances in circuit assemblies

Apparatus and method for compensating clock period elongation durin...

Systems and methods for facilitating testing of integrated circuits

Systems and methods for designing integrated circuits

Systems and methods for reconfiguring scan chains

Method and apparatus for an embedded time domain reflectometry test

System and method for automatic masking of compressed scan chains w...

Method and apparatus for enabling a user to determine whether a def...

Circuit and method for comparing circuit performance between functi...

Apparatus and method for compensating clock period elongation durin...

Programmable hysteresis for boundary-scan testing

Method for determining the impact on test coverage of scan chain pa...

Generating test patterns for testing an integrated circuit

Hierarchically-controlled automatic test pattern generation

Systems and methods for testing receiver terminations in integrated...

Systems and methods for testing tri-state bus drivers

Systems and methods for testing tri-state bus drivers

System and method for evaluating an integrated circuit design

Partitioning integrated circuit hierarchy

Systems and methods for facilitating testing of pads of integrated...

Method and apparatus for measuring the quality of delay test patterns

Systems and methods for facilitating driver strength testing of int...

Method and apparatus for deriving a bounded set of path delay test...

Method and apparatus for testing current sinking/sourcing capabilit...

Systems and methods for facilitating testing of pad drivers of inte...

Systems and methods for facilitating testing of pad receivers of in...

Systems and methods for facilitating automated test equipment funct...

Systems and methods for facilitating testing of pad drivers of inte...

Method and apparatus of boundary scan testing for AC-coupled differ...