Jeffery T. NICHOLS

Person

Marietta, GA, US

People

Patents Grantslast 30 patents

Information Patent Grant
OpenFEC error marking
- Patent number 12,149,352
- Issue date Nov 19, 2024
- Ciena Corporation
- Sebastien Gareau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Precision time protocol using a coherent optical DSP frame
- Patent number 11,552,722
- Issue date Jan 10, 2023
- Ciena Corporation
- Sebastien Gareau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
OpenFEC error marking
- Patent number 11,184,112
- Issue date Nov 23, 2021
- Ciena Corporation
- Sebastien Gareau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Protected transponded services integrated with control plane switch...
- Patent number 10,063,336
- Issue date Aug 28, 2018
- Ciena Corporation
- Jeffrey Scott Moynihan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Scalable switch fabric using optical interconnects
- Patent number 9,980,021
- Issue date May 22, 2018
- Ciena Corporation
- John K. Oltman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Extensible time space switch systems and methods
- Patent number 9,825,883
- Issue date Nov 21, 2017
- Ciena Corporation
- Jeffery Thomas Nichols
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
ODUflex resizing systems and methods
- Patent number 9,538,264
- Issue date Jan 3, 2017
- Ciena Corporation
- Steven Arvo Surek
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Extensible time space switch systems and methods for high capacity...
- Patent number 8,830,993
- Issue date Sep 9, 2014
- Ciena Corporation
- Ian Dublin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuit systems and methods using prime number interleave optimizat...
- Patent number 8,732,358
- Issue date May 20, 2014
- Ciena Corporation
- Jeffery T. Nichols
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for efficient parallel implementation of burst...
- Patent number 8,458,560
- Issue date Jun 4, 2013
- Ciena Corporation
- Jeffery T. Nichols
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pseudo-noise insertion on unacceptable input data sequence in optic...
- Patent number 8,356,233
- Issue date Jan 15, 2013
- Ciena Corporation
- Jeffery Thomas Nichols
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Optical network real time latency measurement systems and methods
- Patent number 8,306,420
- Issue date Nov 6, 2012
- Ciena Corporation
- Richard W. Conklin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for computing the error locator polynomial in...
- Patent number 7,096,408
- Issue date Aug 22, 2006
- CIENA Corporation
- Howard H. Ireland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating bit errors in a forward error c...
- Patent number 7,073,117
- Issue date Jul 4, 2006
- CIENA Corporation
- Howard H. Ireland
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for use in a decoder of a forward error correc...
- Patent number 7,058,876
- Issue date Jun 6, 2006
- CIENA Corporation
- Howard H. Ireland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing syndrome computation in a decod...
- Patent number 7,039,854
- Issue date May 2, 2006
- CIENA Corporation
- Howard H. Ireland
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for generating bit errors with a poisson error...
- Patent number 7,003,708
- Issue date Feb 21, 2006
- CIENA Corporation
- Howard H. Ireland
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for generating parity bits in a forward error...
- Patent number 6,986,097
- Issue date Jan 10, 2006
- CIENA Corporation
- Howard H. Ireland
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
OpenFEC error marking
- Publication number 20250038888
- Publication date Jan 30, 2025
- CIENA CORPORATION
- Sebastien Gareau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
OpenFEC error marking
- Publication number 20240007225
- Publication date Jan 4, 2024
- CIENA CORPORATION
- Sebastien Gareau
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Precision Time Protocol using a coherent optical DSP frame
- Publication number 20220190946
- Publication date Jun 16, 2022
- CIENA CORPORATION
- Sebastien Gareau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE SWITCH FABRIC USING OPTICAL INTERCONNECTS
- Publication number 20170105060
- Publication date Apr 13, 2017
- CIENA CORPORATION
- John K. OLTMAN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ODUFLEX RESIZING SYSTEMS AND METHODS
- Publication number 20160044392
- Publication date Feb 11, 2016
- CIENA CORPORATION
- Steven Arvo SUREK
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CIRCUIT SYSTEMS AND METHODS USING PRIME NUMBER INTERLEAVE OPTIMIZAT...
- Publication number 20140095743
- Publication date Apr 3, 2014
- CIENA CORPORATION
- Jeffery T. Nichols
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENSIBLE TIME SPACE SWITCH SYSTEMS AND METHODS
- Publication number 20110292932
- Publication date Dec 1, 2011
- Jeffery Thomas Nichols
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PSEUDO-NOISE INSERTION ON UNACCEPTABLE INPUT DATA SEQUENCE IN OPTIC...
- Publication number 20110286742
- Publication date Nov 24, 2011
- Jeffery Thomas Nichols
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
OPTICAL NETWORK REAL TIME LATENCY MEASUREMENT SYSTEMS AND METHODS
- Publication number 20110170859
- Publication date Jul 14, 2011
- Richard W. CONKLIN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEMS AND METHODS FOR EFFICIENT PARALLEL IMPLEMENTATION OF BURST...
- Publication number 20090187808
- Publication date Jul 23, 2009
- Jeffery T. Nichols
- H03 - BASIC ELECTRONIC CIRCUITRY

Jeffery T. NICHOLS

Person

Patents Grantslast 30 patents

OpenFEC error marking

Precision time protocol using a coherent optical DSP frame

OpenFEC error marking

Protected transponded services integrated with control plane switch...

Scalable switch fabric using optical interconnects

Extensible time space switch systems and methods

ODUflex resizing systems and methods

Extensible time space switch systems and methods for high capacity...

Circuit systems and methods using prime number interleave optimizat...

Systems and methods for efficient parallel implementation of burst...

Pseudo-noise insertion on unacceptable input data sequence in optic...

Optical network real time latency measurement systems and methods

Method and apparatus for computing the error locator polynomial in...

Method and apparatus for generating bit errors in a forward error c...

Method and apparatus for use in a decoder of a forward error correc...

Method and apparatus for performing syndrome computation in a decod...

Method and apparatus for generating bit errors with a poisson error...

Method and apparatus for generating parity bits in a forward error...

Patents Applicationslast 30 patents

OpenFEC error marking

OpenFEC error marking

Precision Time Protocol using a coherent optical DSP frame

SCALABLE SWITCH FABRIC USING OPTICAL INTERCONNECTS

ODUFLEX RESIZING SYSTEMS AND METHODS

CIRCUIT SYSTEMS AND METHODS USING PRIME NUMBER INTERLEAVE OPTIMIZAT...

EXTENSIBLE TIME SPACE SWITCH SYSTEMS AND METHODS

PSEUDO-NOISE INSERTION ON UNACCEPTABLE INPUT DATA SEQUENCE IN OPTIC...

OPTICAL NETWORK REAL TIME LATENCY MEASUREMENT SYSTEMS AND METHODS

SYSTEMS AND METHODS FOR EFFICIENT PARALLEL IMPLEMENTATION OF BURST...