Jeffrey Chee

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Capacitor top plate over source/drain to form a 1T memory device
- Patent number 8,716,081
- Issue date May 6, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid orientation substrate with stress layer
- Patent number 8,274,115
- Issue date Sep 25, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacture of an integrated circuit system with self-ali...
- Patent number 8,053,327
- Issue date Nov 8, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Shailendra Mishra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell structure and method for fabrication thereof
- Patent number 7,999,300
- Issue date Aug 16, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Zhao Lun
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Integrated circuit having a plurality of MOSFET devices
- Patent number 7,932,178
- Issue date Apr 26, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Lee Wee Teo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to lower work function of gate electrode through Ge implanta...
- Patent number 7,101,746
- Issue date Sep 5, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Tze Ho Simon Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to selectively form poly SiGe P type electrode and polysilic...
- Patent number 6,872,608
- Issue date Mar 29, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Tze Ho Chan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MEMORY CELL STRUCTURE AND METHOD FOR FABRICATION THEREOF
- Publication number 20100187587
- Publication date Jul 29, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Zhao LUN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID ORIENTATION SUBSTRATE WITH STRESS LAYER
- Publication number 20090236663
- Publication date Sep 24, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAPACITOR TOP PLATE OVER SOURCE/DRAIN TO FORM A 1T MEMORY DEVICE
- Publication number 20080224228
- Publication date Sep 18, 2008
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT HAVING A PLURALITY OF MOSFET DEVICES
- Publication number 20080157223
- Publication date Jul 3, 2008
- Chartered Semiconductor Manufacturing LTD.
- Lee Wee Teo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH ISOLATION
- Publication number 20080150074
- Publication date Jun 26, 2008
- Chartered Semiconductor Manufacturing LTD.
- Shailendra Mishra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to selectively form SiGe P type electrode and polysilicon N...
- Publication number 20060205138
- Publication date Sep 14, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Tze Ho Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to lower work function of gate electrode through Ge implanta...
- Publication number 20050095773
- Publication date May 5, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Tze Ho Simon Chan
- H01 - BASIC ELECTRIC ELEMENTS

Jeffrey Chee

Person

Patents Grantslast 30 patents

Capacitor top plate over source/drain to form a 1T memory device

Hybrid orientation substrate with stress layer

Method of manufacture of an integrated circuit system with self-ali...

Memory cell structure and method for fabrication thereof

Integrated circuit having a plurality of MOSFET devices

Method to lower work function of gate electrode through Ge implanta...

Method to selectively form poly SiGe P type electrode and polysilic...

Patents Applicationslast 30 patents

MEMORY CELL STRUCTURE AND METHOD FOR FABRICATION THEREOF

HYBRID ORIENTATION SUBSTRATE WITH STRESS LAYER

CAPACITOR TOP PLATE OVER SOURCE/DRAIN TO FORM A 1T MEMORY DEVICE

INTEGRATED CIRCUIT HAVING A PLURALITY OF MOSFET DEVICES

INTEGRATED CIRCUIT SYSTEM WITH ISOLATION

Method to selectively form SiGe P type electrode and polysilicon N...

Method to lower work function of gate electrode through Ge implanta...