Jeffrey J. Cook

Person

Hillboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems, methods, and apparatuses for heterogeneous computing
- Patent number 12,135,981
- Issue date Nov 5, 2024
- Intel Corporation
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine learning accelerator mechanism
- Patent number 12,039,435
- Issue date Jul 16, 2024
- Intel Corporation
- Amit Bleiweiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatuses for heterogeneous computing
- Patent number 11,693,691
- Issue date Jul 4, 2023
- Intel Corporation
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatuses for heterogeneous computing
- Patent number 11,416,281
- Issue date Aug 16, 2022
- Intel Corporation
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for adaptable and efficient lane-wise tensor p...
- Patent number 11,379,229
- Issue date Jul 5, 2022
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine learning accelerator mechanism
- Patent number 11,373,088
- Issue date Jun 28, 2022
- Intel Corporation
- Amit Bleiweiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for symbolic store address generation...
- Patent number 11,188,341
- Issue date Nov 30, 2021
- Intel Corporation
- Jeffrey J. Cook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatuses for heterogeneous computing
- Patent number 11,093,277
- Issue date Aug 17, 2021
- Intel Corporation
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for translation cache management in binary translation...
- Patent number 10,983,773
- Issue date Apr 20, 2021
- Intel Corporation
- Paul Caprioli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a high throughput parallel co-processor an...
- Patent number 10,915,328
- Issue date Feb 9, 2021
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gather-scatter cache architecture having plurality of tag and data...
- Patent number 10,896,141
- Issue date Jan 19, 2021
- Intel Corporation
- Jeffrey J. Cook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture and method for data parallel single program multiple d...
- Patent number 10,831,505
- Issue date Nov 10, 2020
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for adaptable and efficient lane-wise tensor p...
- Patent number 10,776,110
- Issue date Sep 15, 2020
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, apparatuses, and methods for a hardware and software syste...
- Patent number 10,725,755
- Issue date Jul 28, 2020
- Intel Corporation
- David J. Sager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for translation cache management in binary translation...
- Patent number 10,282,182
- Issue date May 7, 2019
- Intel Corporation
- Paul Caprioli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerated interlane vector reduction instructions
- Patent number 10,209,989
- Issue date Feb 19, 2019
- Intel Corporation
- Paul Caprioli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware for miss handling from a translation protection data struc...
- Patent number 10,089,244
- Issue date Oct 2, 2018
- Intel Corporation
- Paul Caprioli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementation of processor trace in a processor that supports bina...
- Patent number 9,934,124
- Issue date Apr 3, 2018
- Intel Corporation
- Furat F. Afram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using control flow data structures to direct and track instruction...
- Patent number 9,880,842
- Issue date Jan 30, 2018
- Intel Corporation
- Jayaram Bobba
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerated interlane vector reduction instructions
- Patent number 9,588,766
- Issue date Mar 7, 2017
- Intel Corporation
- Paul Caprioli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, apparatuses, and methods for a hardware and software syste...
- Patent number 9,189,233
- Issue date Nov 17, 2015
- Intel Corporation
- Ruchira Sasanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Analyzing potential benefits of vectorization
- Patent number 9,170,789
- Issue date Oct 27, 2015
- Intel Corporation
- Ruchira Sasanka
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MACHINE LEARNING ACCELERATOR MECHANISM
- Publication number 20240403620
- Publication date Dec 5, 2024
- Intel Corporation
- Amit Bleiweiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING
- Publication number 20230418655
- Publication date Dec 28, 2023
- Intel Corporation
- Rajesh M. SANKARAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONOUS MICROTHREADING
- Publication number 20230315455
- Publication date Oct 5, 2023
- Intel Corporation
- David B. SHEFFIELD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONOUS MICROTHREADING
- Publication number 20230315458
- Publication date Oct 5, 2023
- Intel Corporation
- Shreesha SRINATH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONOUS MICROTHREADING
- Publication number 20230315460
- Publication date Oct 5, 2023
- Intel Corporation
- David B. SHEFFIELD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONOUS MICROTHREADING
- Publication number 20230315572
- Publication date Oct 5, 2023
- Intel Corporation
- David B. SHEFFIELD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONOUS MICROTHREADING
- Publication number 20230315462
- Publication date Oct 5, 2023
- Intel Corporation
- David B. SHEFFIELD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONOUS MICROTHREADING
- Publication number 20230315444
- Publication date Oct 5, 2023
- Intel Corporation
- David B. SHEFFIELD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONOUS MICROTHREADING
- Publication number 20230315459
- Publication date Oct 5, 2023
- Intel Corporation
- David B. SHEFFIELD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONOUS MICROTHREADING
- Publication number 20230315445
- Publication date Oct 5, 2023
- Intel Corporation
- David B. SHEFFIELD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONOUS MICROTHREADING
- Publication number 20230315461
- Publication date Oct 5, 2023
- Intel Corporation
- David B. SHEFFIELD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING ACCELERATOR MECHANISM
- Publication number 20230053289
- Publication date Feb 16, 2023
- Intel Corporation
- Amit Bleiweiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING
- Publication number 20220164218
- Publication date May 26, 2022
- Intel Corporation
- Rajesh M. SANKARAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING
- Publication number 20200401440
- Publication date Dec 24, 2020
- Intel Corporation
- Rajesh M. SANKARAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR ADAPTABLE AND EFFICIENT LANE-WISE TENSOR P...
- Publication number 20200364045
- Publication date Nov 19, 2020
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Symbolic Store Address Generation...
- Publication number 20200310817
- Publication date Oct 1, 2020
- Intel Corporation
- Jeffrey J. Cook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Gather-Scatter Cache Architecture For Single Program Multiple Data...
- Publication number 20200310992
- Publication date Oct 1, 2020
- Intel Corporation
- Jeffrey J. Cook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR A HIGH THROUGHPUT PARALLEL CO-PROCESSOR AN...
- Publication number 20200192676
- Publication date Jun 18, 2020
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR ADAPTABLE AND EFFICIENT LANE-WISE TENSOR P...
- Publication number 20200104126
- Publication date Apr 2, 2020
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE AND METHOD FOR DATA PARALLEL SINGLE PROGRAM MULTIPLE D...
- Publication number 20200104139
- Publication date Apr 2, 2020
- Intel Corporation
- Jonathan Pearce
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING
- Publication number 20190347125
- Publication date Nov 14, 2019
- Intel Corporation
- Rajesh M. SANKARAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR TRANSLATION CACHE MANAGEMENT IN BINARY TRANSLATION...
- Publication number 20190235849
- Publication date Aug 1, 2019
- Intel Corporation
- Paul Caprioli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING ACCELERATOR MECHANISM
- Publication number 20190205737
- Publication date Jul 4, 2019
- Intel Corporation
- Amit Bleiweiss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE FOR MISS HANDLING FROM A TRANSLATION PROTECTION DATA STRUC...
- Publication number 20180285283
- Publication date Oct 4, 2018
- Intel Corporation
- Paul Caprioli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR TRANSLATION CACHE MANAGEMENT IN BINARY TRANSLATION...
- Publication number 20180088921
- Publication date Mar 29, 2018
- Intel Corporation
- Paul Caprioli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTE...
- Publication number 20180060049
- Publication date Mar 1, 2018
- Intel Corporation
- DAVID J. SAGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATED INTERLANE VECTOR REDUCTION INSTRUCTIONS
- Publication number 20170242699
- Publication date Aug 24, 2017
- Intel Corporation
- PAUL CAPRIOLI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementation Of Processor Trace In A Processor That Supports Bina...
- Publication number 20160357658
- Publication date Dec 8, 2016
- Intel Corporation
- Furat F. Afram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRACKING CONTROL FLOW OF INSTRUCTIONS
- Publication number 20140281424
- Publication date Sep 18, 2014
- Jayaram Bobba
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ANALYZING POTENTIAL BENEFITS OF VECTORIZATION
- Publication number 20140258677
- Publication date Sep 11, 2014
- Ruchira Sasanka
- G06 - COMPUTING CALCULATING COUNTING

Jeffrey J. Cook

Person

Patents Grantslast 30 patents

Systems, methods, and apparatuses for heterogeneous computing

Machine learning accelerator mechanism

Systems, methods, and apparatuses for heterogeneous computing

Systems, methods, and apparatuses for heterogeneous computing

Apparatus and method for adaptable and efficient lane-wise tensor p...

Machine learning accelerator mechanism

System, apparatus and method for symbolic store address generation...

Systems, methods, and apparatuses for heterogeneous computing

Technologies for translation cache management in binary translation...

Apparatus and method for a high throughput parallel co-processor an...

Gather-scatter cache architecture having plurality of tag and data...

Architecture and method for data parallel single program multiple d...

Apparatus and method for adaptable and efficient lane-wise tensor p...

Systems, apparatuses, and methods for a hardware and software syste...

Technologies for translation cache management in binary translation...

Accelerated interlane vector reduction instructions

Hardware for miss handling from a translation protection data struc...

Implementation of processor trace in a processor that supports bina...

Using control flow data structures to direct and track instruction...

Accelerated interlane vector reduction instructions

Systems, apparatuses, and methods for a hardware and software syste...

Analyzing potential benefits of vectorization

Patents Applicationslast 30 patents

MACHINE LEARNING ACCELERATOR MECHANISM

SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING

SYNCHRONOUS MICROTHREADING

SYNCHRONOUS MICROTHREADING

SYNCHRONOUS MICROTHREADING

SYNCHRONOUS MICROTHREADING

SYNCHRONOUS MICROTHREADING

SYNCHRONOUS MICROTHREADING

SYNCHRONOUS MICROTHREADING

SYNCHRONOUS MICROTHREADING

SYNCHRONOUS MICROTHREADING

MACHINE LEARNING ACCELERATOR MECHANISM

SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING

SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING

APPARATUS AND METHOD FOR ADAPTABLE AND EFFICIENT LANE-WISE TENSOR P...

System, Apparatus And Method For Symbolic Store Address Generation...

Gather-Scatter Cache Architecture For Single Program Multiple Data...

APPARATUS AND METHOD FOR A HIGH THROUGHPUT PARALLEL CO-PROCESSOR AN...

APPARATUS AND METHOD FOR ADAPTABLE AND EFFICIENT LANE-WISE TENSOR P...

ARCHITECTURE AND METHOD FOR DATA PARALLEL SINGLE PROGRAM MULTIPLE D...

SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING

TECHNOLOGIES FOR TRANSLATION CACHE MANAGEMENT IN BINARY TRANSLATION...

MACHINE LEARNING ACCELERATOR MECHANISM

HARDWARE FOR MISS HANDLING FROM A TRANSLATION PROTECTION DATA STRUC...

TECHNOLOGIES FOR TRANSLATION CACHE MANAGEMENT IN BINARY TRANSLATION...

SYSTEMS, APPARATUSES, AND METHODS FOR A HARDWARE AND SOFTWARE SYSTE...

ACCELERATED INTERLANE VECTOR REDUCTION INSTRUCTIONS

Implementation Of Processor Trace In A Processor That Supports Bina...

TRACKING CONTROL FLOW OF INSTRUCTIONS

ANALYZING POTENTIAL BENEFITS OF VECTORIZATION