Jeffrey K. Whitt

Person

Colorado Springs, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and structure for correlating multiple test outputs of an i...
- Patent number 8,775,888
- Issue date Jul 8, 2014
- LSI Corporation
- Eugene Saghi
- G01 - MEASURING TESTING
Information Patent Grant
Methods and structure for utilizing external interfaces used during...
- Patent number 8,745,457
- Issue date Jun 3, 2014
- LSI Corporation
- Eugene Saghi
- G01 - MEASURING TESTING
Information Patent Grant
Methods and structure for correlation of test signals routed using...
- Patent number 8,738,979
- Issue date May 27, 2014
- LSI Corporation
- Paul J. Smith
- G01 - MEASURING TESTING
Information Patent Grant
Methods and structure for storing errors for error recovery in a ha...
- Patent number 8,589,722
- Issue date Nov 19, 2013
- LSI Corporation
- Joshua P. Sinykin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for detecting a failure in a SAS/SATA topology
- Patent number 8,527,815
- Issue date Sep 3, 2013
- LSI Corporation
- Jeffrey K. Whitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System debug of input/output virtualization device
- Patent number 8,176,207
- Issue date May 8, 2012
- LSI Corporation
- Richard I. Solomon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for translation of data formats between multi...
- Patent number 8,108,574
- Issue date Jan 31, 2012
- LSI Corporation
- John C. Udell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduction of latency in store and forward architectures utilizing m...
- Patent number 7,991,927
- Issue date Aug 2, 2011
- LSI Corporation
- John Udell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for capture of flow control errors in clock d...
- Patent number 7,913,124
- Issue date Mar 22, 2011
- LSI Corporation
- John C. Udell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FIFO peek access
- Patent number 7,773,453
- Issue date Aug 10, 2010
- LSI Corporation
- Jerzy Szwagrzyk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable reset circuit for a phase-locked loop
- Patent number 7,719,368
- Issue date May 18, 2010
- Agere Systems Inc.
- Paul Jeffrey Smith
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Maintaining dynamic count of FIFO contents in multiple clock domains
- Patent number 7,646,668
- Issue date Jan 12, 2010
- LSI Corporation
- John Udell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and/or apparatus for implementing enhanced device identifica...
- Patent number 7,082,522
- Issue date Jul 25, 2006
- LSI Logic Corporation
- Jeffrey K. Whitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Characteristic image of electrical data bus
- Patent number 7,028,233
- Issue date Apr 11, 2006
- LSI Logic Corporation
- Andrew Hadley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for measuring bus frequency
- Patent number 6,882,952
- Issue date Apr 19, 2005
- LSI Logic Corporation
- Andrew J. Hadley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-channel interface controller for enabling a host to interface...
- Patent number 6,851,007
- Issue date Feb 1, 2005
- LSI Logic Corporation
- Jeffrey K. Whitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PCI bus system testing and verification apparatus and method
- Patent number 6,587,813
- Issue date Jul 1, 2003
- LSI Logic Corporation
- Jeffrey K. Whitt
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND STRUCTURE FOR CORRELATION OF TEST SIGNALS ROUTED USING...
- Publication number 20130262946
- Publication date Oct 3, 2013
- Paul J. Smith
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND STRUCTURE FOR UTILIZING EXTERNAL INTERFACES USED DURING...
- Publication number 20130257512
- Publication date Oct 3, 2013
- Eugene Saghi
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND STRUCTURE FOR CORRELATING MULTIPLE TEST OUTPUTS OF AN I...
- Publication number 20130262945
- Publication date Oct 3, 2013
- Eugene Saghi
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND STRUCTURE FOR STORING ERRORS FOR ERROR RECOVERY IN A HA...
- Publication number 20120290875
- Publication date Nov 15, 2012
- LSI Corporation
- Joshua P. Sinykin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR DETECTING A FAILURE IN A SAS/SATA TOPOLOGY
- Publication number 20120072772
- Publication date Mar 22, 2012
- LSI Corporation
- Jeffrey K. Whitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE RESET CIRCUIT FOR A PHASE-LOCKED LOOP
- Publication number 20100124256
- Publication date May 20, 2010
- Paul Jeffrey Smith
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS AND METHODS FOR CAPTURE OF FLOW CONTROL ERRORS IN CLOCK D...
- Publication number 20100088554
- Publication date Apr 8, 2010
- John C. Udell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS FOR TRANSLATION OF DATA FORMATS BETWEEN MULTI...
- Publication number 20100088438
- Publication date Apr 8, 2010
- John C. Udell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIFO PEEK ACCESS
- Publication number 20090251986
- Publication date Oct 8, 2009
- Jerzy Szwagrzyk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAINTAINING DYNAMIC COUNT OF FIFO CONTENTS IN MULTIPLE CLOCK DOMAINS
- Publication number 20090244993
- Publication date Oct 1, 2009
- John Udell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System debug of input/output virtualization device
- Publication number 20090248937
- Publication date Oct 1, 2009
- Richard I. Solomon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCTION OF LATENCY IN STORE AND FORWARD ARCHITECTURES UTILIZING M...
- Publication number 20090248968
- Publication date Oct 1, 2009
- John Udell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR EXTERNAL FIFO ACCELERATION
- Publication number 20090248919
- Publication date Oct 1, 2009
- Jerzy Szwagrzyk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RAID storage controller assist circuit, systems and methods
- Publication number 20060143506
- Publication date Jun 29, 2006
- LSI Logic Corporation
- Jeffrey K. Whitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Characteristic image of electrical data bus
- Publication number 20040133835
- Publication date Jul 8, 2004
- Andrew Hadley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and/or apparatus for implementing enhanced device identifica...
- Publication number 20040010678
- Publication date Jan 15, 2004
- LSI Logic Corporation
- Jeffrey K. Whitt
- G06 - COMPUTING CALCULATING COUNTING

Jeffrey K. Whitt

Person

Patents Grantslast 30 patents

Methods and structure for correlating multiple test outputs of an i...

Methods and structure for utilizing external interfaces used during...

Methods and structure for correlation of test signals routed using...

Methods and structure for storing errors for error recovery in a ha...

Method for detecting a failure in a SAS/SATA topology

System debug of input/output virtualization device

Apparatus and methods for translation of data formats between multi...

Reduction of latency in store and forward architectures utilizing m...

Apparatus and methods for capture of flow control errors in clock d...

FIFO peek access

Configurable reset circuit for a phase-locked loop

Maintaining dynamic count of FIFO contents in multiple clock domains

Method and/or apparatus for implementing enhanced device identifica...

Characteristic image of electrical data bus

System and method for measuring bus frequency

Multi-channel interface controller for enabling a host to interface...

PCI bus system testing and verification apparatus and method

Patents Applicationslast 30 patents

METHODS AND STRUCTURE FOR CORRELATION OF TEST SIGNALS ROUTED USING...

METHODS AND STRUCTURE FOR UTILIZING EXTERNAL INTERFACES USED DURING...

METHODS AND STRUCTURE FOR CORRELATING MULTIPLE TEST OUTPUTS OF AN I...

METHODS AND STRUCTURE FOR STORING ERRORS FOR ERROR RECOVERY IN A HA...

METHOD FOR DETECTING A FAILURE IN A SAS/SATA TOPOLOGY

CONFIGURABLE RESET CIRCUIT FOR A PHASE-LOCKED LOOP

APPARATUS AND METHODS FOR CAPTURE OF FLOW CONTROL ERRORS IN CLOCK D...

APPARATUS AND METHODS FOR TRANSLATION OF DATA FORMATS BETWEEN MULTI...

FIFO PEEK ACCESS

MAINTAINING DYNAMIC COUNT OF FIFO CONTENTS IN MULTIPLE CLOCK DOMAINS

System debug of input/output virtualization device

REDUCTION OF LATENCY IN STORE AND FORWARD ARCHITECTURES UTILIZING M...

METHOD FOR EXTERNAL FIFO ACCELERATION

RAID storage controller assist circuit, systems and methods

Characteristic image of electrical data bus

Method and/or apparatus for implementing enhanced device identifica...