Jeffrey L. Nye

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for computational transport network-on-chip (NoC)
- Patent number 11,082,327
- Issue date Aug 3, 2021
- ARTERIS, INC.
- Jeffrey L. Nye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for mixed instruction multiple data (xIMD) comp...
- Patent number 10,990,394
- Issue date Apr 27, 2021
- Intel Corporation
- Jeffrey L. Nye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Live migration of hardware accelerated applications
- Patent number 10,489,193
- Issue date Nov 26, 2019
- Altera Corporation
- Jeffrey L. Nye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Live migration of hardware accelerated applications
- Patent number 10,169,065
- Issue date Jan 1, 2019
- Altera Corporation
- Jeffrey L. Nye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with control node circuitry and processing circu...
- Patent number 9,552,206
- Issue date Jan 24, 2017
- Texas Instruments Incorporated
- William M. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processes, circuits, devices, and systems for branch prediction and...
- Patent number 7,752,426
- Issue date Jul 6, 2010
- Texas Instruments Incorporated
- Jeffrey L. Nye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Full/selector output from one of plural flag generation count outputs
- Patent number 7,587,532
- Issue date Sep 8, 2009
- Texas Instruments Incorporated
- Jeffrey L. Nye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache lock mechanism with speculative allocation
- Patent number 7,266,648
- Issue date Sep 4, 2007
- Intel Corporation
- Edwin R. Sutanto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache lock mechanism with speculative allocation
- Patent number 6,986,010
- Issue date Jan 10, 2006
- Intel Corporation
- Edwin R. Sutanto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two computer access circuit using address translation into common r...
- Patent number 6,189,077
- Issue date Feb 13, 2001
- Texas Instruments Incorporated
- Iain C. Robertson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multifunctional access devices, systems and methods
- Patent number 6,154,824
- Issue date Nov 28, 2000
- Texas Instruments Incorporated
- Iain C. Robertson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using prioritized interrupt callback routines to process different...
- Patent number 5,940,610
- Issue date Aug 17, 1999
- Brooktree Corporation
- David C. Baker
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Graphics processor writing to shadow register at predetermined addr...
- Patent number 5,696,923
- Issue date Dec 9, 1997
- Texas Instruments Incorporated
- Iain C. Robertson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access circuit with address translation performing auto incr...
- Patent number 5,696,924
- Issue date Dec 9, 1997
- Texas Instruments Incorporated
- Iain C. Robertson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics computer system having a second palette shadowing data in...
- Patent number 5,636,335
- Issue date Jun 3, 1997
- Texas Instruments Incorporated
- Iain C. Robertson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multifunctional access devices, systems and methods
- Patent number 5,546,553
- Issue date Aug 13, 1996
- Texas Instruments Incorporated
- Iain C. Robertson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data cache access for signal processing systems
- Patent number 5,386,538
- Issue date Jan 31, 1995
- Texas Instruments Incorporated
- Jeffrey L. Nye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Video interface palette, systems and method
- Patent number 5,371,517
- Issue date Dec 6, 1994
- Texas Instruments Incorporated
- Louis Izzi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer graphics systems, palette devices and methods for shift cl...
- Patent number 5,341,470
- Issue date Aug 23, 1994
- Texas Instruments Incorporated
- Richard D. Simpson
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Packed bus selection of multiple pixel depths in palette devices, s...
- Patent number 5,327,159
- Issue date Jul 5, 1994
- Texas Instruments Incorporated
- Jerry R. Van Aken
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Devices, systems and methods for palette pass-through mode
- Patent number 5,309,551
- Issue date May 3, 1994
- Texas Instruments Incorporated
- Karl M. Guttag
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Controlled delay devices, systems and methods
- Patent number 5,293,468
- Issue date Mar 8, 1994
- Texas Instruments Incorporated
- Jeffrey L. Nye
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Graphics systems, palettes and methods with combined video and shif...
- Patent number 5,287,100
- Issue date Feb 15, 1994
- Texas Instruments Incorporated
- Karl M. Guttag
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Memory mapped interface between host computer and graphics system
- Patent number 5,280,579
- Issue date Jan 18, 1994
- Texas Instruments Incorporated
- Jeffrey L. Nye
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR COMPUTATIONAL TRANSPORT NETWORK-ON-CHIP (NoC)
- Publication number 20200213217
- Publication date Jul 2, 2020
- Arteris, Inc
- Jeffrey L. NYE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LIVE MIGRATION OF HARDWARE ACCELERATED APPLICATIONS
- Publication number 20190129744
- Publication date May 2, 2019
- Altera Corporation
- Jeffrey L. Nye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR MIXED INSTRUCTION MULTIPLE DATA (xIMD) COMP...
- Publication number 20190095208
- Publication date Mar 28, 2019
- Intel Corporation
- Jeffrey L. Nye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-PERFORMANCE, SCALABLE MUTLICORE HARDWARE AND SOFTWARE SYSTEM
- Publication number 20120131309
- Publication date May 24, 2012
- TEXAS INSTRUMENTS INCORPORATED
- William M. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CORE ARCHITECTURE WITH HARDWARE MESSAGING
- Publication number 20070180310
- Publication date Aug 2, 2007
- Texas Instruments, Inc.
- William M. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for adaptive buffer sizing
- Publication number 20060179186
- Publication date Aug 10, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Jeffrey L. Nye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processes, circuits, devices, and systems for branch prediction and...
- Publication number 20060095750
- Publication date May 4, 2006
- Jeffrey L. Nye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache lock mechanism with speculative allocation
- Publication number 20060064551
- Publication date Mar 23, 2006
- Edwin R. Sutanto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache lock mechanism with speculative allocation
- Publication number 20040117573
- Publication date Jun 17, 2004
- Edwin R. Sutanto
- G06 - COMPUTING CALCULATING COUNTING

Jeffrey L. Nye

Person

Patents Grantslast 30 patents

System and method for computational transport network-on-chip (NoC)

Systems and methods for mixed instruction multiple data (xIMD) comp...

Live migration of hardware accelerated applications

Live migration of hardware accelerated applications

Integrated circuit with control node circuitry and processing circu...

Processes, circuits, devices, and systems for branch prediction and...

Full/selector output from one of plural flag generation count outputs

Cache lock mechanism with speculative allocation

Cache lock mechanism with speculative allocation

Two computer access circuit using address translation into common r...

Multifunctional access devices, systems and methods

Using prioritized interrupt callback routines to process different...

Graphics processor writing to shadow register at predetermined addr...

Memory access circuit with address translation performing auto incr...

Graphics computer system having a second palette shadowing data in...

Multifunctional access devices, systems and methods

Data cache access for signal processing systems

Video interface palette, systems and method

Computer graphics systems, palette devices and methods for shift cl...

Packed bus selection of multiple pixel depths in palette devices, s...

Devices, systems and methods for palette pass-through mode

Controlled delay devices, systems and methods

Graphics systems, palettes and methods with combined video and shif...

Memory mapped interface between host computer and graphics system

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR COMPUTATIONAL TRANSPORT NETWORK-ON-CHIP (NoC)

LIVE MIGRATION OF HARDWARE ACCELERATED APPLICATIONS

SYSTEMS AND METHODS FOR MIXED INSTRUCTION MULTIPLE DATA (xIMD) COMP...

HIGH-PERFORMANCE, SCALABLE MUTLICORE HARDWARE AND SOFTWARE SYSTEM

MULTI-CORE ARCHITECTURE WITH HARDWARE MESSAGING

Method and apparatus for adaptive buffer sizing

Processes, circuits, devices, and systems for branch prediction and...

Cache lock mechanism with speculative allocation

Cache lock mechanism with speculative allocation