Jeffrey Orion Pritchard

Person

Santa Cruz, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
High-level language code sequence optimization for implementing pro...
- Patent number 9,329,847
- Issue date May 3, 2016
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for importing hardware design and generating...
- Patent number 8,977,531
- Issue date Mar 10, 2015
- Altera Corporation
- James M. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tool selection and implementation of port adapters
- Patent number 8,706,931
- Issue date Apr 22, 2014
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for importing hardware design and generating...
- Patent number 8,606,558
- Issue date Dec 10, 2013
- Altera Corporation
- James M. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-level language code sequence optimization for implementing pro...
- Patent number 8,578,356
- Issue date Nov 5, 2013
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Allocating hardware resources for high-level language code sequences
- Patent number 8,543,949
- Issue date Sep 24, 2013
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduling optimization of aliased pointers for implementation on p...
- Patent number 8,291,396
- Issue date Oct 16, 2012
- Altera Corporation
- David James Lau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selection of port adapters for clock crossing boundaries
- Patent number 8,286,025
- Issue date Oct 9, 2012
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for importing hardware design and generating...
- Patent number 8,234,101
- Issue date Jul 31, 2012
- Altera Corporation
- James M. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adapter allowing unaligned access to memory
- Patent number 8,219,785
- Issue date Jul 10, 2012
- Altera Corporation
- Timothy P. Allen
- G11 - INFORMATION STORAGE
Information Patent Grant
Tool with graphical interconnect matrix
- Patent number 8,191,035
- Issue date May 29, 2012
- Altera Corporation
- David Van Brink
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Allocating hardware resources for high-level language code sequences
- Patent number 8,161,444
- Issue date Apr 17, 2012
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for implementing parameterizable processors a...
- Patent number 8,156,455
- Issue date Apr 10, 2012
- Altera Corporaton
- Tim Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for implementing parameterizable processors a...
- Patent number 8,132,132
- Issue date Mar 6, 2012
- Altera Corporation
- Tim Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Master and slave side arbitrators associated with programmable chip...
- Patent number 8,082,378
- Issue date Dec 20, 2011
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for implementing parameterizable processors a...
- Patent number 8,037,434
- Issue date Oct 11, 2011
- Altera Corporation
- Tim Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for importing hardware design and generating...
- Patent number 7,890,317
- Issue date Feb 15, 2011
- Altera Corporation
- James M. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-level language code sequence optimization for implementing pro...
- Patent number 7,873,953
- Issue date Jan 18, 2011
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System memory map decoder logic
- Patent number 7,809,861
- Issue date Oct 5, 2010
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design tool with graphical interconnect matrix
- Patent number 7,802,221
- Issue date Sep 21, 2010
- Altera Corporation
- David Van Brink
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design tool clock domain crossing management
- Patent number 7,779,286
- Issue date Aug 17, 2010
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Master and slave side arbitrators associated with programmable chip...
- Patent number 7,769,934
- Issue date Aug 3, 2010
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design tool selection and implementation of port adapters
- Patent number 7,769,929
- Issue date Aug 3, 2010
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic test component generation and inclusion into simulation t...
- Patent number 7,730,435
- Issue date Jun 1, 2010
- Altera Corporation
- Jeffrey Orion Pritchard
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus for implementing parameterizable processors a...
- Patent number 7,676,784
- Issue date Mar 9, 2010
- Altera Corporation
- Tim Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for controlling multiple master/slave connect...
- Patent number 7,675,931
- Issue date Mar 9, 2010
- Altera Corporation
- Jeffrey Orion Pritchard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and apparatus for allowing simultaneous memory accesses in...
- Patent number 7,636,817
- Issue date Dec 22, 2009
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for selective comment assertion
- Patent number 7,493,584
- Issue date Feb 17, 2009
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable chip bus arbitration logic
- Patent number 7,395,360
- Issue date Jul 1, 2008
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating components on a programmable device using a high-level l...
- Patent number 7,370,311
- Issue date May 6, 2008
- Altera Corporation
- Jeffrey Orion Pritchard
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHODS FOR IMPORTING HARDWARE DESIGN AND GENERATING...
- Publication number 20080147359
- Publication date Jun 19, 2008
- Altera Corporation
- James M. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR IMPLEMENTING PARAMETERIZABLE PROCESSORS A...
- Publication number 20080134127
- Publication date Jun 5, 2008
- Altera Corporation
- Tim Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic test component generation and inclusion into simulation t...
- Publication number 20070234247
- Publication date Oct 4, 2007
- Altera Corporation
- Jeffrey Orion Pritchard
- G01 - MEASURING TESTING
Information Patent Application
Methods and apparatus for implementing parameterizable processors a...
- Publication number 20060190907
- Publication date Aug 24, 2006
- Altera Corporation
- Tim Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for implementing parameterizable processors a...
- Publication number 20060053404
- Publication date Mar 9, 2006
- Altera Corporation
- Tim Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for implementing parameterizable processors a...
- Publication number 20060036988
- Publication date Feb 16, 2006
- Altera Corporation
- Tim Allen
- G06 - COMPUTING CALCULATING COUNTING

Jeffrey Orion Pritchard

Person

Patents Grantslast 30 patents

High-level language code sequence optimization for implementing pro...

Apparatus and methods for importing hardware design and generating...

Tool selection and implementation of port adapters

Apparatus and methods for importing hardware design and generating...

High-level language code sequence optimization for implementing pro...

Allocating hardware resources for high-level language code sequences

Scheduling optimization of aliased pointers for implementation on p...

Selection of port adapters for clock crossing boundaries

Apparatus and methods for importing hardware design and generating...

Adapter allowing unaligned access to memory

Tool with graphical interconnect matrix

Allocating hardware resources for high-level language code sequences

Methods and apparatus for implementing parameterizable processors a...

Methods and apparatus for implementing parameterizable processors a...

Master and slave side arbitrators associated with programmable chip...

Methods and apparatus for implementing parameterizable processors a...

Apparatus and methods for importing hardware design and generating...

High-level language code sequence optimization for implementing pro...

System memory map decoder logic

Design tool with graphical interconnect matrix

Design tool clock domain crossing management

Master and slave side arbitrators associated with programmable chip...

Design tool selection and implementation of port adapters

Automatic test component generation and inclusion into simulation t...

Methods and apparatus for implementing parameterizable processors a...

Methods and apparatus for controlling multiple master/slave connect...

Methods and apparatus for allowing simultaneous memory accesses in...

Methods and apparatus for selective comment assertion

Programmable chip bus arbitration logic

Generating components on a programmable device using a high-level l...

Patents Applicationslast 30 patents

APPARATUS AND METHODS FOR IMPORTING HARDWARE DESIGN AND GENERATING...

METHODS AND APPARATUS FOR IMPLEMENTING PARAMETERIZABLE PROCESSORS A...

Automatic test component generation and inclusion into simulation t...

Methods and apparatus for implementing parameterizable processors a...

Methods and apparatus for implementing parameterizable processors a...

Methods and apparatus for implementing parameterizable processors a...