Jeffrey P. Soreff

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Model order reduction in transistor level timing
- Patent number 10,031,988
- Issue date Jul 24, 2018
- International Business Machines Corporation
- Robert J. Allen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modeling loading effects of a transistor network
- Patent number 8,655,634
- Issue date Feb 18, 2014
- International Business Machines Corporation
- David J. Hathaway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay model construction in the presence of multiple input switchin...
- Patent number 8,607,176
- Issue date Dec 10, 2013
- International Business Machines Corporation
- Jeffrey P. Soreff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing point selection for a static timing analysis in the presence...
- Patent number 8,201,120
- Issue date Jun 12, 2012
- International Business Machines Corporation
- Jeffrey P. Soreff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for common history pessimism relief during static...
- Patent number 8,141,014
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device history based delay variation adjustment during static timin...
- Patent number 8,108,816
- Issue date Jan 31, 2012
- International Business Machines Corporation
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for improved hierarchical analysis of electronic...
- Patent number 7,870,515
- Issue date Jan 11, 2011
- International Business Machines Corporation
- Philip G. Shephard, III
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pulse waveform timing in EinsTLT templates
- Patent number 7,643,981
- Issue date Jan 5, 2010
- International Business Machines Corporation
- Sang Y. Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for modeling logical circuit blocks including tra...
- Patent number 7,552,040
- Issue date Jun 23, 2009
- International Business Machines Corporation
- Barry Lee Dorfman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid linear wire model approach to tuning transistor widths of ci...
- Patent number 7,325,210
- Issue date Jan 29, 2008
- International Business Machines Corporation
- Vasant Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for modeling latch transparency
- Patent number 7,225,419
- Issue date May 29, 2007
- International Business Machines Corporation
- Erwin Behnen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of timing model abstraction for circuits containing simultan...
- Patent number 7,191,419
- Issue date Mar 13, 2007
- International Business Machines Corporation
- Jeffrey Paul Soreff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for modeling latch transparency
- Patent number 7,080,335
- Issue date Jul 18, 2006
- International Business Machines Corporation
- Erwin Behnen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for reducing RC parasitics in interconnect networks of an in...
- Patent number 6,763,504
- Issue date Jul 13, 2004
- International Business Machines Corporation
- Vasant B. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced pessimism clock gating tests for a timing analysis tool
- Patent number 6,718,523
- Issue date Apr 6, 2004
- International Business Machines Corporation
- David J. Hathaway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for performing slew dependent signal bounding...
- Patent number 6,430,731
- Issue date Aug 6, 2002
- International Business Machines Corporation
- Jin-Fuw Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for evaluating the timing of digital machines with statistic...
- Patent number 5,365,463
- Issue date Nov 15, 1994
- International Business Machines Corporation
- Wilm E. Donath
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MODEL ORDER REDUCTION IN TRANSISTOR LEVEL TIMING
- Publication number 20160085890
- Publication date Mar 24, 2016
- International Business Machines Corporation
- Robert J. ALLEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay Model Construction In The Presence Of Multiple Input Switchin...
- Publication number 20120266119
- Publication date Oct 18, 2012
- International Business Machines Corporation
- Jeffrey P. Soreff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modeling Loading Effects of a Transistor Network
- Publication number 20110224965
- Publication date Sep 15, 2011
- International Business Machines Corporation
- David J. Hathaway
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Timing Point Selection For A Static Timing Analysis In The Presence...
- Publication number 20110167395
- Publication date Jul 7, 2011
- International Business Machines Corporation
- Jeffrey P. Soreff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR COMMON HISTORY PESSIMISM RELIEF DURING STATIC...
- Publication number 20110035714
- Publication date Feb 10, 2011
- International Business Machines Corporation
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR DEVICE HISTORY BASED DELAY VARIATION ADJUSTME...
- Publication number 20100318951
- Publication date Dec 16, 2010
- International Business Machines Corporation
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Improved Hierarchical Analysis of Electronic...
- Publication number 20090183130
- Publication date Jul 16, 2009
- Philip G. Shephard, III
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR CALCULATING CIRCUIT BLOCK DELAY AND TRANSITION TIMES...
- Publication number 20080177517
- Publication date Jul 24, 2008
- Barry Lee Dorfman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple mode approach to building static timing models for digital...
- Publication number 20070234253
- Publication date Oct 4, 2007
- International Business Machines Corporation
- Jeffrey P. Soreff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hybrid linear wire model approach to tuning transistor widths of ci...
- Publication number 20060206845
- Publication date Sep 14, 2006
- International Business Machines Corporation
- Vasant Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of timing model abstraction for circuits containing simultan...
- Publication number 20060031797
- Publication date Feb 9, 2006
- International Business Machines Corporation
- Jeffrey Paul Soreff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pulse waveform timing in EinsTLT templates
- Publication number 20060020443
- Publication date Jan 26, 2006
- International Business Machines Corporation
- Sang Y. Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods for modeling latch transparency
- Publication number 20050071790
- Publication date Mar 31, 2005
- Erwin Behnen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods for modeling latch transparency
- Publication number 20050071794
- Publication date Mar 31, 2005
- Erwin Behnen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for modeling logical circuit blocks including tra...
- Publication number 20040162716
- Publication date Aug 19, 2004
- International Business Machines Corporation
- Barry Lee Dorfman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reduced pessimism clock gating tests for a timing analysis tool
- Publication number 20030009733
- Publication date Jan 9, 2003
- David J. Hathaway
- G06 - COMPUTING CALCULATING COUNTING

Jeffrey P. Soreff

Person

Patents Grantslast 30 patents

Model order reduction in transistor level timing

Modeling loading effects of a transistor network

Delay model construction in the presence of multiple input switchin...

Timing point selection for a static timing analysis in the presence...

System and method for common history pessimism relief during static...

Device history based delay variation adjustment during static timin...

System and method for improved hierarchical analysis of electronic...

Pulse waveform timing in EinsTLT templates

Method and system for modeling logical circuit blocks including tra...

Hybrid linear wire model approach to tuning transistor widths of ci...

Methods for modeling latch transparency

Method of timing model abstraction for circuits containing simultan...

Methods for modeling latch transparency

Method for reducing RC parasitics in interconnect networks of an in...

Reduced pessimism clock gating tests for a timing analysis tool

Methods and apparatus for performing slew dependent signal bounding...

Method for evaluating the timing of digital machines with statistic...

Patents Applicationslast 30 patents

MODEL ORDER REDUCTION IN TRANSISTOR LEVEL TIMING

Delay Model Construction In The Presence Of Multiple Input Switchin...

Modeling Loading Effects of a Transistor Network

Timing Point Selection For A Static Timing Analysis In The Presence...

SYSTEM AND METHOD FOR COMMON HISTORY PESSIMISM RELIEF DURING STATIC...

SYSTEM AND METHOD FOR DEVICE HISTORY BASED DELAY VARIATION ADJUSTME...

System and Method for Improved Hierarchical Analysis of Electronic...

TECHNIQUES FOR CALCULATING CIRCUIT BLOCK DELAY AND TRANSITION TIMES...

Multiple mode approach to building static timing models for digital...

Hybrid linear wire model approach to tuning transistor widths of ci...

Method of timing model abstraction for circuits containing simultan...

Pulse waveform timing in EinsTLT templates

Methods for modeling latch transparency

Methods for modeling latch transparency

Method and system for modeling logical circuit blocks including tra...

Reduced pessimism clock gating tests for a timing analysis tool