Jeffrey S. Brown

Person

Ft. Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Parallel interface pattern modification for addressing signal integ...
- Patent number 9,148,171
- Issue date Sep 29, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Marek J. Marasch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for decreasing signal integrity noise by using va...
- Patent number 8,890,564
- Issue date Nov 18, 2014
- LSI Corporation
- Jay D. Harker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Overshoot suppression for input/output buffers
- Patent number 8,773,192
- Issue date Jul 8, 2014
- LSI Corporation
- Mark F. Turner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optimization of library slew ratio based circuit
- Patent number 8,667,438
- Issue date Mar 4, 2014
- LSI Corporation
- Jeffrey Scott Brown
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
On-chip power supply monitoring using a network of modulators
- Patent number 8,471,720
- Issue date Jun 25, 2013
- LSI Corporation
- Mark Franklin Turner
- G01 - MEASURING TESTING
Information Patent Grant
Fine-grained clock skew tuning in an integrated circuit
- Patent number 8,432,210
- Issue date Apr 30, 2013
- LSI Corporation
- Jeffrey S. Brown
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Optimization of library slew ratio based circuit
- Patent number 8,418,102
- Issue date Apr 9, 2013
- LSI Corporation
- Jeffrey Scott Brown
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power grid optimization
- Patent number 8,336,018
- Issue date Dec 18, 2012
- LSI Corporation
- Mark F. Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input/output core design and method of manufacture therefor
- Patent number 8,289,051
- Issue date Oct 16, 2012
- LSI Corporation
- Mark F. Turner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Architecturally independent noise sensitivity analysis of integrate...
- Patent number 8,239,801
- Issue date Aug 7, 2012
- LSI Corporation
- Mark F. Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Closed-loop soft error rate sensitivity control
- Patent number 8,232,819
- Issue date Jul 31, 2012
- LSI Corporation
- Mark F. Turner
- G11 - INFORMATION STORAGE
Information Patent Grant
Sequential element low power scan implementation
- Patent number 8,209,573
- Issue date Jun 26, 2012
- LSI Corporation
- Jeff S. Brown
- G01 - MEASURING TESTING
Information Patent Grant
Granular channel width for power optimization
- Patent number 8,196,086
- Issue date Jun 5, 2012
- LSI Corporation
- Jeffrey S. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modulated clock, an IC including the modulated clock and a method o...
- Patent number 8,135,976
- Issue date Mar 13, 2012
- LSI Corporation
- Jeff S. Brown
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Transistor bit cell ROM architecture
- Patent number 8,125,815
- Issue date Feb 28, 2012
- LSI Corporation
- Jeffrey S. Brown
- G11 - INFORMATION STORAGE
Information Patent Grant
D flip-flop having enhanced immunity to single-event upsets and met...
- Patent number 8,115,531
- Issue date Feb 14, 2012
- LSI Corporation
- Jeff S. Brown
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of generating a restricted inline resistive fault pattern an...
- Patent number 8,055,467
- Issue date Nov 8, 2011
- LSI Corporation
- Jeff S. Brown
- G01 - MEASURING TESTING
Information Patent Grant
Energy efficient memory access technique for single ended bit cells
- Patent number 7,990,796
- Issue date Aug 2, 2011
- LSI Corporation
- Jeffrey S. Brown
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual path static timing analysis
- Patent number 7,966,592
- Issue date Jun 21, 2011
- LSI Corporation
- Jeffrey S. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch and DFF design with improved soft error rate and a method of...
- Patent number 7,932,762
- Issue date Apr 26, 2011
- LSI Corporation
- Mark F. Turner
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Redistribution of current demand and reduction of power and DCAP
- Patent number 7,818,695
- Issue date Oct 19, 2010
- LSI Corporation
- Jonathan W. Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Row decode driver gradient design in a memory device
- Patent number 7,787,325
- Issue date Aug 31, 2010
- LSI Corporation
- Jeffrey S. Brown
- G11 - INFORMATION STORAGE
Information Patent Grant
Metal programmable self-timed memories
- Patent number 7,746,722
- Issue date Jun 29, 2010
- LSI Corporation
- Jeffrey Scott Brown
- G11 - INFORMATION STORAGE
Information Patent Grant
Testable tristate bus keeper
- Patent number 7,676,716
- Issue date Mar 9, 2010
- LSI Corporation
- Jeffrey S. Brown
- G01 - MEASURING TESTING
Information Patent Grant
Leakage optimized memory
- Patent number 7,567,478
- Issue date Jul 28, 2009
- LSI Corporation
- Jeffrey S. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory data inversion architecture for minimizing power consumption
- Patent number 7,525,864
- Issue date Apr 28, 2009
- LSI Corporation
- Jeffrey S. Brown
- G11 - INFORMATION STORAGE
Information Patent Grant
Cell library management for power optimization
- Patent number 7,496,867
- Issue date Feb 24, 2009
- LSI Corporation
- Mark F. Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Metal programmable self-timed memories
- Patent number 7,400,543
- Issue date Jul 15, 2008
- LSI Logic Corporation
- Jeffrey Scott Brown
- G11 - INFORMATION STORAGE
Information Patent Grant
Device and method for using a lessened load to measure signal skew...
- Patent number 7,219,270
- Issue date May 15, 2007
- LSI Logic Corporation
- Jeffrey S. Brown
- G11 - INFORMATION STORAGE
Information Patent Grant
Type configurable memory methodology for use with metal programmabl...
- Patent number 7,143,386
- Issue date Nov 28, 2006
- LSI Logic Corporation
- Jeffrey Scott Brown
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
OVERSHOOT SUPPRESSION FOR INPUT/OUTPUT BUFFERS
- Publication number 20140145775
- Publication date May 29, 2014
- LSI Corporation
- Mark F. Turner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR DECREASING SIGNAL INTEGRITY NOISE BY USING VA...
- Publication number 20130249591
- Publication date Sep 26, 2013
- LSI Corporation
- Jay D. Harker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT
- Publication number 20130152036
- Publication date Jun 13, 2013
- LSI Corporation
- Jeffrey Scott Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR
- Publication number 20120194217
- Publication date Aug 2, 2012
- LSI Corporation
- Mark F. Turner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR
- Publication number 20120119785
- Publication date May 17, 2012
- LSI Corporation
- Mark F. Turner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
On-chip Power Supply Monitoring Using a Network of Modulators
- Publication number 20120119788
- Publication date May 17, 2012
- Mark Franklin Turner
- G01 - MEASURING TESTING
Information Patent Application
Fine-grained Clock Skew Tuning in an Integrated Circuit
- Publication number 20120105123
- Publication date May 3, 2012
- Jeffrey S. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUILT-IN SELF-TEST CIRCUIT-BASED RADIATION SENSOR, RADIATION SENSIN...
- Publication number 20120065919
- Publication date Mar 15, 2012
- LSI Corporation
- Jeff S. Brown
- G01 - MEASURING TESTING
Information Patent Application
GRANULAR CHANNEL WIDTH FOR POWER OPTIMIZATION
- Publication number 20120023473
- Publication date Jan 26, 2012
- Jeffrey S. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE MEMORY ARCHITECTURE FOR STATIC POWER REDUCTION AND METHOD...
- Publication number 20120008450
- Publication date Jan 12, 2012
- LSI Corporation
- Mark F. Turner
- G11 - INFORMATION STORAGE
Information Patent Application
POWER GRID OPTIMIZATION
- Publication number 20110304052
- Publication date Dec 15, 2011
- Mark F. Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOSED-LOOP SOFT ERROR RATE SENSITIVITY CONTROL
- Publication number 20110128035
- Publication date Jun 2, 2011
- Mark F. Turner
- G11 - INFORMATION STORAGE
Information Patent Application
ANALYZER AND METHODS FOR ARCHITECTURALLY INDEPENDENT NOISE SENSITIV...
- Publication number 20100169850
- Publication date Jul 1, 2010
- LSI Corporation
- Mark F. Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSISTOR BIT CELL ROM ARCHITECTURE
- Publication number 20100157649
- Publication date Jun 24, 2010
- Jeffrey S. Brown
- G11 - INFORMATION STORAGE
Information Patent Application
SEQUENTIAL ELEMENT LOW POWER SCAN IMPLEMENTATION
- Publication number 20100162058
- Publication date Jun 24, 2010
- LSI Corporation
- Jeff S. Brown
- G01 - MEASURING TESTING
Information Patent Application
LATCH AND DFF DESIGN WITH IMPROVED SOFT ERROR RATE AND A METHOD OF...
- Publication number 20100156494
- Publication date Jun 24, 2010
- LSI Corporation
- Mark F. Turner
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD OF GENERATING A RESTRICTED INLINE RESISTIVE FAULT PATTERN AN...
- Publication number 20100153056
- Publication date Jun 17, 2010
- LSI Corporation
- Jeff S. Brown
- G01 - MEASURING TESTING
Information Patent Application
MODULATED CLOCK, AN IC INCLUDING THE MODULATED CLOCK AND A METHOD O...
- Publication number 20100150271
- Publication date Jun 17, 2010
- LSI Corporation
- Jeff S. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTABLE TRISTATE BUS KEEPER
- Publication number 20100007371
- Publication date Jan 14, 2010
- LSI Corporation
- Jeffrey S. Brown
- G01 - MEASURING TESTING
Information Patent Application
ROW DECODE DRIVER GRADIENT DESIGN IN A MEMORY DEVICE
- Publication number 20090285047
- Publication date Nov 19, 2009
- Jeffrey S. Brown
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS OF CELL ASSOCIATION FOR AUTOMATED DISTANCE MANAGEMENT IN IN...
- Publication number 20090288053
- Publication date Nov 19, 2009
- Jeffrey S. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT
- Publication number 20090267671
- Publication date Oct 29, 2009
- Jeffrey Scott Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDISTRIBUTION OF CURRENT DEMAND AND REDUCTION OF POWER AND DCAP
- Publication number 20090164956
- Publication date Jun 25, 2009
- Jonathan W. Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL PATH STATIC TIMING ANALYSIS
- Publication number 20090144682
- Publication date Jun 4, 2009
- Jeffrey S. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEAKAGE OPTIMIZED MEMORY
- Publication number 20090091999
- Publication date Apr 9, 2009
- Jeffrey S. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METAL PROGRAMMABLE SELF-TIMED MEMORIES
- Publication number 20080253206
- Publication date Oct 16, 2008
- Jeffrey Scott Brown
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DATA INVERSION ARCHITECTURE FOR MINIMIZING POWER CONSUMPTION
- Publication number 20080247257
- Publication date Oct 9, 2008
- Jeffrey S. Brown
- G11 - INFORMATION STORAGE
Information Patent Application
Energy efficient memory access technique for single ended bit cells
- Publication number 20080250257
- Publication date Oct 9, 2008
- LSI CORPORATION
- Jeffrey S. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cell library management for power optimization
- Publication number 20080244474
- Publication date Oct 2, 2008
- LSI Logic Corporation
- Mark F. Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Conductor stack shifting
- Publication number 20050198608
- Publication date Sep 8, 2005
- Jeffrey S. Brown
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Jeffrey S. Brown

Person

Patents Grantslast 30 patents

Parallel interface pattern modification for addressing signal integ...

System and method for decreasing signal integrity noise by using va...

Overshoot suppression for input/output buffers

Optimization of library slew ratio based circuit

On-chip power supply monitoring using a network of modulators

Fine-grained clock skew tuning in an integrated circuit

Optimization of library slew ratio based circuit

Power grid optimization

Input/output core design and method of manufacture therefor

Architecturally independent noise sensitivity analysis of integrate...

Closed-loop soft error rate sensitivity control

Sequential element low power scan implementation

Granular channel width for power optimization

Modulated clock, an IC including the modulated clock and a method o...

Transistor bit cell ROM architecture

D flip-flop having enhanced immunity to single-event upsets and met...

Method of generating a restricted inline resistive fault pattern an...

Energy efficient memory access technique for single ended bit cells

Dual path static timing analysis

Latch and DFF design with improved soft error rate and a method of...

Redistribution of current demand and reduction of power and DCAP

Row decode driver gradient design in a memory device

Metal programmable self-timed memories

Testable tristate bus keeper

Leakage optimized memory

Memory data inversion architecture for minimizing power consumption

Cell library management for power optimization

Metal programmable self-timed memories

Device and method for using a lessened load to measure signal skew...

Type configurable memory methodology for use with metal programmabl...

Patents Applicationslast 30 patents

OVERSHOOT SUPPRESSION FOR INPUT/OUTPUT BUFFERS

SYSTEM AND METHOD FOR DECREASING SIGNAL INTEGRITY NOISE BY USING VA...

OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT

INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR

INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR

On-chip Power Supply Monitoring Using a Network of Modulators

Fine-grained Clock Skew Tuning in an Integrated Circuit

BUILT-IN SELF-TEST CIRCUIT-BASED RADIATION SENSOR, RADIATION SENSIN...

GRANULAR CHANNEL WIDTH FOR POWER OPTIMIZATION

FLEXIBLE MEMORY ARCHITECTURE FOR STATIC POWER REDUCTION AND METHOD...

POWER GRID OPTIMIZATION

CLOSED-LOOP SOFT ERROR RATE SENSITIVITY CONTROL

ANALYZER AND METHODS FOR ARCHITECTURALLY INDEPENDENT NOISE SENSITIV...

TRANSISTOR BIT CELL ROM ARCHITECTURE

SEQUENTIAL ELEMENT LOW POWER SCAN IMPLEMENTATION

LATCH AND DFF DESIGN WITH IMPROVED SOFT ERROR RATE AND A METHOD OF...

METHOD OF GENERATING A RESTRICTED INLINE RESISTIVE FAULT PATTERN AN...

MODULATED CLOCK, AN IC INCLUDING THE MODULATED CLOCK AND A METHOD O...

TESTABLE TRISTATE BUS KEEPER

ROW DECODE DRIVER GRADIENT DESIGN IN A MEMORY DEVICE

METHODS OF CELL ASSOCIATION FOR AUTOMATED DISTANCE MANAGEMENT IN IN...

OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT

REDISTRIBUTION OF CURRENT DEMAND AND REDUCTION OF POWER AND DCAP

DUAL PATH STATIC TIMING ANALYSIS

LEAKAGE OPTIMIZED MEMORY

METAL PROGRAMMABLE SELF-TIMED MEMORIES

MEMORY DATA INVERSION ARCHITECTURE FOR MINIMIZING POWER CONSUMPTION

Energy efficient memory access technique for single ended bit cells

Cell library management for power optimization

Conductor stack shifting