Jeffrey S. McNeil

Person

Nampa, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
All level coarse/fine programming of memory cells
- Patent number 12,224,012
- Issue date Feb 11, 2025
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallelized defect detection across multiple sub-blocks in a memor...
- Patent number 12,217,799
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Paing Z. Htet
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrent slow-fast memory cell programming
- Patent number 12,211,552
- Issue date Jan 28, 2025
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrent programming of retired wordline cells with dummy data
- Patent number 12,170,113
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory sub-system scan
- Patent number 12,148,484
- Issue date Nov 19, 2024
- Micron Technology, Inc.
- Vamsi Pavan Rayaprolu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices for multiple read operations
- Patent number 12,142,343
- Issue date Nov 12, 2024
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Program command generation with dummy data generation at a memory d...
- Patent number 12,141,437
- Issue date Nov 12, 2024
- Micron Technology, Inc.
- Jeremy Binfet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programming selective word lines during an erase operation in a mem...
- Patent number 12,131,028
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-tier defect scan management
- Patent number 12,105,967
- Issue date Oct 1, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Copyback clear command for performing a scan and read in a memory d...
- Patent number 12,105,961
- Issue date Oct 1, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated command to calibrate read voltage level
- Patent number 12,073,891
- Issue date Aug 27, 2024
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
On-die cross-temperature management for a memory device
- Patent number 12,067,290
- Issue date Aug 20, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-pass corrective programming for memory cells that store multipl...
- Patent number 12,068,034
- Issue date Aug 20, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Partitioned memory having error detection capability
- Patent number 12,026,052
- Issue date Jul 2, 2024
- Kishore K. Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Workload-based scan optimization
- Patent number 11,977,778
- Issue date May 7, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing program verifies for multi-level NAND cells
- Patent number 11,887,680
- Issue date Jan 30, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using duplicate data for improving error correction capability
- Patent number 11,861,233
- Issue date Jan 2, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read calibration based on ranges of program/erase cycles
- Patent number 11,797,216
- Issue date Oct 24, 2023
- Micron Technology, Inc.
- Vamsi Pavan Rayaprolu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Separate partition for buffer and snapshot memory
- Patent number 11,789,629
- Issue date Oct 17, 2023
- Micron Technology, Inc.
- Kishore K. Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Threshold voltage based on program/erase cycles
- Patent number 11,776,629
- Issue date Oct 3, 2023
- Micron Technology, Inc.
- Niccolo′ Righetti
- G11 - INFORMATION STORAGE
Information Patent Grant
Partitions within snapshot memory for buffer and snapshot memory
- Patent number 11,775,208
- Issue date Oct 3, 2023
- Micron Technology, Inc.
- Kishore K. Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices for multiple read operations
- Patent number 11,756,594
- Issue date Sep 12, 2023
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus for discharging control gates after performing a sensing...
- Patent number 11,710,523
- Issue date Jul 25, 2023
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G11 - INFORMATION STORAGE
Information Patent Grant
Read voltage calibration for copyback operation
- Patent number 11,694,763
- Issue date Jul 4, 2023
- Micron Technology, Inc.
- Kishore K. Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read window based on program/erase cycles
- Patent number 11,688,479
- Issue date Jun 27, 2023
- Micron Technology, Inc.
- Vamsi Pavan Rayaprolu
- G11 - INFORMATION STORAGE
Information Patent Grant
Threshold voltage distribution adjustment for buffer
- Patent number 11,663,104
- Issue date May 30, 2023
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global-local read calibration
- Patent number 11,636,908
- Issue date Apr 25, 2023
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Overwriting at a memory system
- Patent number 11,605,434
- Issue date Mar 14, 2023
- Micron Technology, Inc.
- Jonathan S. Parry
- G11 - INFORMATION STORAGE
Information Patent Grant
Data management during a copyback operation
- Patent number 11,556,267
- Issue date Jan 17, 2023
- Micron Technology, Inc.
- Kishore K. Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sub-system scan
- Patent number 11,527,294
- Issue date Dec 13, 2022
- Micron Technology, Inc.
- Vamsi Pavan Rayaprolu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ALL LEVEL COARSE/FINE PROGRAMMING OF MEMORY CELLS
- Publication number 20250149093
- Publication date May 8, 2025
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Application
PARALLELIZED DEFECT DETECTION ACROSS MULTIPLE SUB-BLOCKS IN A MEMOR...
- Publication number 20250140317
- Publication date May 1, 2025
- Micron Technology, Inc.
- Paing Z. Htet
- G11 - INFORMATION STORAGE
Information Patent Application
CONCURRENT PROGRAMMING OF RETIRED WORDLINE CELLS WITH DUMMY DATA
- Publication number 20250078932
- Publication date Mar 6, 2025
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING SELECTIVE WORD LINES DURING AN ERASE OPERATION IN A MEM...
- Publication number 20250053301
- Publication date Feb 13, 2025
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAM COMMAND GENERATION WITH DUMMY DATA GENERATION AT A MEMORY D...
- Publication number 20250028447
- Publication date Jan 23, 2025
- Micron Technology, Inc.
- Jeremy Binfet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES FOR MULTIPLE READ OPERATIONS
- Publication number 20250029641
- Publication date Jan 23, 2025
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY D...
- Publication number 20250004645
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-TIER DEFECT SCAN MANAGEMENT
- Publication number 20240402922
- Publication date Dec 5, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ VOLTAGE LEVEL BIN SELECTION
- Publication number 20240395338
- Publication date Nov 28, 2024
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
ON-DIE CROSS-TEMPERATURE MANAGEMENT FOR A MEMORY DEVICE
- Publication number 20240370206
- Publication date Nov 7, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING PILLAR VOLTAGE USING WORDLINE BOOST VOLTAGE AND SELECT...
- Publication number 20240339158
- Publication date Oct 10, 2024
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAM VOLTAGE SELECTION DURING ALL LEVELS PROGRAMMING OF A MEMORY...
- Publication number 20240295970
- Publication date Sep 5, 2024
- Micron Technology, Inc.
- Sheyang Ning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WORKLOAD-BASED SCAN OPTIMIZATION
- Publication number 20240248646
- Publication date Jul 25, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VOLATILE DATA STORAGE IN NAND MEMORY
- Publication number 20240177755
- Publication date May 30, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING DUPLICATE DATA FOR IMPROVING ERROR CORRECTION CAPABILITY
- Publication number 20240134571
- Publication date Apr 25, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-TIER DEFECT SCAN MANAGEMENT
- Publication number 20240069765
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-PASS CORRECTIVE PROGRAMMING FOR MEMORY CELLS THAT STORE MULTIPL...
- Publication number 20240071510
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
GENERATING SEMI-SOFT BIT DATA DURING CORRECTIVE READ OPERATIONS IN...
- Publication number 20240071435
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Phong Sy Nguyen
- G11 - INFORMATION STORAGE
Information Patent Application
ESTABLISHING BITLINE, WORDLINE AND BOOST VOLTAGES TO MANAGE A MAXIM...
- Publication number 20240005987
- Publication date Jan 4, 2024
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES FOR MULTIPLE READ OPERATIONS
- Publication number 20230386533
- Publication date Nov 30, 2023
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
CRYPTOGRAPHIC BLOCK LOCKING IN A NON-VOLATILE MEMORY DEVICE
- Publication number 20230384951
- Publication date Nov 30, 2023
- Micron Technology, Inc.
- Jeremy BINFET
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IDENTIFYING A MOST RECENTLY PROGRAMMED PAGE DURING MEMORY DEVICE IN...
- Publication number 20230335199
- Publication date Oct 19, 2023
- Micron Technology, Inc.
- Jeremy BINFET
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALL LEVEL COARSE/FINE PROGRAMMING OF MEMORY CELLS
- Publication number 20230317171
- Publication date Oct 5, 2023
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Application
WORKLOAD-BASED SCAN OPTIMIZATION
- Publication number 20230305744
- Publication date Sep 28, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENT SLOW-FAST MEMORY CELL PROGRAMMING
- Publication number 20230307055
- Publication date Sep 28, 2023
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Application
PARALLELIZED DEFECT DETECTION ACROSS MULTIPLE SUB-BLOCKS IN A MEMOR...
- Publication number 20230307053
- Publication date Sep 28, 2023
- Micron Technology, Inc.
- Paing Z. Htet
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING SELECTIVE WORD LINES DURING AN ERASE OPERATION IN A MEM...
- Publication number 20230289062
- Publication date Sep 14, 2023
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVELY PROGRAMMING RETIRED WORDLINES OF A MEMORY DEVICE
- Publication number 20230214133
- Publication date Jul 6, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL CELL AND MULTI-SUB-BLOCK PROGRAMMING IN A MEMORY DEVICE
- Publication number 20230207019
- Publication date Jun 29, 2023
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Application
CONCURRENT SCAN OPERATION ON MULTIPLE BLOCKS IN A MEMORY DEVICE
- Publication number 20230206992
- Publication date Jun 29, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE

Jeffrey S. McNeil

Person

Patents Grantslast 30 patents

All level coarse/fine programming of memory cells

Parallelized defect detection across multiple sub-blocks in a memor...

Concurrent slow-fast memory cell programming

Concurrent programming of retired wordline cells with dummy data

Memory sub-system scan

Memory devices for multiple read operations

Program command generation with dummy data generation at a memory d...

Programming selective word lines during an erase operation in a mem...

Two-tier defect scan management

Copyback clear command for performing a scan and read in a memory d...

Integrated command to calibrate read voltage level

On-die cross-temperature management for a memory device

Two-pass corrective programming for memory cells that store multipl...

Partitioned memory having error detection capability

Workload-based scan optimization

Reducing program verifies for multi-level NAND cells

Using duplicate data for improving error correction capability

Read calibration based on ranges of program/erase cycles

Separate partition for buffer and snapshot memory

Threshold voltage based on program/erase cycles

Partitions within snapshot memory for buffer and snapshot memory

Memory devices for multiple read operations

Apparatus for discharging control gates after performing a sensing...

Read voltage calibration for copyback operation

Read window based on program/erase cycles

Threshold voltage distribution adjustment for buffer

Global-local read calibration

Overwriting at a memory system

Data management during a copyback operation

Memory sub-system scan

Patents Applicationslast 30 patents

ALL LEVEL COARSE/FINE PROGRAMMING OF MEMORY CELLS

PARALLELIZED DEFECT DETECTION ACROSS MULTIPLE SUB-BLOCKS IN A MEMOR...

CONCURRENT PROGRAMMING OF RETIRED WORDLINE CELLS WITH DUMMY DATA

PROGRAMMING SELECTIVE WORD LINES DURING AN ERASE OPERATION IN A MEM...

PROGRAM COMMAND GENERATION WITH DUMMY DATA GENERATION AT A MEMORY D...

MEMORY DEVICES FOR MULTIPLE READ OPERATIONS

COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY D...

TWO-TIER DEFECT SCAN MANAGEMENT

READ VOLTAGE LEVEL BIN SELECTION

ON-DIE CROSS-TEMPERATURE MANAGEMENT FOR A MEMORY DEVICE

CONTROLLING PILLAR VOLTAGE USING WORDLINE BOOST VOLTAGE AND SELECT...

PROGRAM VOLTAGE SELECTION DURING ALL LEVELS PROGRAMMING OF A MEMORY...

WORKLOAD-BASED SCAN OPTIMIZATION

VOLATILE DATA STORAGE IN NAND MEMORY

USING DUPLICATE DATA FOR IMPROVING ERROR CORRECTION CAPABILITY

TWO-TIER DEFECT SCAN MANAGEMENT

TWO-PASS CORRECTIVE PROGRAMMING FOR MEMORY CELLS THAT STORE MULTIPL...

GENERATING SEMI-SOFT BIT DATA DURING CORRECTIVE READ OPERATIONS IN...

ESTABLISHING BITLINE, WORDLINE AND BOOST VOLTAGES TO MANAGE A MAXIM...

MEMORY DEVICES FOR MULTIPLE READ OPERATIONS

CRYPTOGRAPHIC BLOCK LOCKING IN A NON-VOLATILE MEMORY DEVICE

IDENTIFYING A MOST RECENTLY PROGRAMMED PAGE DURING MEMORY DEVICE IN...

ALL LEVEL COARSE/FINE PROGRAMMING OF MEMORY CELLS

WORKLOAD-BASED SCAN OPTIMIZATION

CONCURRENT SLOW-FAST MEMORY CELL PROGRAMMING

PARALLELIZED DEFECT DETECTION ACROSS MULTIPLE SUB-BLOCKS IN A MEMOR...

PROGRAMMING SELECTIVE WORD LINES DURING AN ERASE OPERATION IN A MEM...

SELECTIVELY PROGRAMMING RETIRED WORDLINES OF A MEMORY DEVICE

MULTI-LEVEL CELL AND MULTI-SUB-BLOCK PROGRAMMING IN A MEMORY DEVICE

CONCURRENT SCAN OPERATION ON MULTIPLE BLOCKS IN A MEMORY DEVICE