Jeffrey Schulz

Person

Milpitas, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Seemingly monolithic interface between separate integrated circuit die
- Patent number 12,191,893
- Issue date Jan 7, 2025
- Altera Corporation
- David W. Mendel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface bridge between integrated circuit die
- Patent number 12,135,667
- Issue date Nov 5, 2024
- Altera Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface bridge between integrated circuit die
- Patent number 11,693,810
- Issue date Jul 4, 2023
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Periphery shoreline augmentation for integrated circuits
- Patent number 11,449,247
- Issue date Sep 20, 2022
- Intel Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface bridge between integrated circuit die
- Patent number 11,237,998
- Issue date Feb 1, 2022
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serial memory interface circuitry for programmable integrated circuits
- Patent number 11,101,930
- Issue date Aug 24, 2021
- Altera Corporation
- Jeffrey Schulz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interface bridge between integrated circuit die
- Patent number 11,100,029
- Issue date Aug 24, 2021
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Seemingly monolithic interface between separate integrated circuit die
- Patent number 11,075,648
- Issue date Jul 27, 2021
- Intel Corporation
- David W. Mendel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Periphery shoreline augmentation for integrated circuits
- Patent number 10,871,906
- Issue date Dec 22, 2020
- Intel Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable integrated circuits with in-operation reconfiguration...
- Patent number 10,591,544
- Issue date Mar 17, 2020
- Altera Corporation
- Dana How
- G01 - MEASURING TESTING
Information Patent Grant
Serial memory interface circuitry for programmable integrated circuits
- Patent number 10,491,333
- Issue date Nov 26, 2019
- Altera Corporation
- Jeffrey Schulz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Interface bridge between integrated circuit die
- Patent number 10,445,278
- Issue date Oct 15, 2019
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Seemingly monolithic interface between separate integrated circuit die
- Patent number 10,439,639
- Issue date Oct 8, 2019
- Intel Corporation
- David W. Mendel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mixed redundancy scheme for inter-die interconnects in a multichip...
- Patent number 10,082,541
- Issue date Sep 25, 2018
- Altera Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mixed redundancy scheme for inter-die interconnects in a multichip...
- Patent number 10,031,182
- Issue date Jul 24, 2018
- Altera Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatuses for optimizing power management on an integr...
- Patent number 9,735,778
- Issue date Aug 15, 2017
- Jeffrey Schulz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Serial memory interface circuitry for programmable integrated circuits
- Patent number 9,712,186
- Issue date Jul 18, 2017
- Altera Corporation
- Jeffrey Schulz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit with bonding circuits for bonding memory control...
- Patent number 9,558,131
- Issue date Jan 31, 2017
- Altera Corporation
- Jeffrey Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transaction handling between soft logic and hard logic components o...
- Patent number 9,424,073
- Issue date Aug 23, 2016
- Altera Corporation
- Jeffrey Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for operating a multi-port memory system
- Patent number 9,343,124
- Issue date May 17, 2016
- Altera Corporation
- Caroline Ssu-Min Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for scalable cross point switching using 3-D die...
- Patent number 9,276,582
- Issue date Mar 1, 2016
- Altera Corporation
- Jeffrey Schulz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory controller interface with adjustable port widths
- Patent number 9,244,867
- Issue date Jan 26, 2016
- Altera Corporation
- Jeffrey Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controllers with dynamic port priority assignment capabilities
- Patent number 9,208,109
- Issue date Dec 8, 2015
- Altera Corporation
- Michael H. M. Chu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuit for scalable cross point switching using 3-D die...
- Patent number 9,077,338
- Issue date Jul 7, 2015
- Altera Corporation
- Jeffrey Schulz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for providing memory controllers with memory ac...
- Patent number 9,032,162
- Issue date May 12, 2015
- Altera Corporation
- Ching-Chi Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for providing memory controllers with scheduler...
- Patent number 8,930,641
- Issue date Jan 6, 2015
- Altera Corporation
- Ravish Kapasi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Double Bump Design for Multiple Purpose IO Connections
- Publication number 20250125296
- Publication date Apr 17, 2025
- Krishna Bharath Kolluru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Interface Bridge Between Integrated Circuit Die
- Publication number 20250021506
- Publication date Jan 16, 2025
- Altera Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE
- Publication number 20230305982
- Publication date Sep 28, 2023
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Input Output Banks of a Programmable Logic Device
- Publication number 20230140547
- Publication date May 4, 2023
- Intel Corporation
- Terence Magee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Source Synchronous Partition of an SDRAM Controller Subsystem
- Publication number 20230123826
- Publication date Apr 20, 2023
- Intel Corporation
- Terence Magee
- G11 - INFORMATION STORAGE
Information Patent Application
Techniques For Synchronous Accesses To Storage Circuits
- Publication number 20230118912
- Publication date Apr 20, 2023
- Intel Corporation
- Jeffrey Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR REDUCING CONGESTION ON NETWORK-ON-CHIP
- Publication number 20220405453
- Publication date Dec 22, 2022
- Rahul Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEEMINGLY MONOLITHIC INTERFACE BETWEEN SEPARATE INTEGRATED CIRCUIT DIE
- Publication number 20220190843
- Publication date Jun 16, 2022
- Intel Corporation
- David W. Mendel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE
- Publication number 20220121595
- Publication date Apr 21, 2022
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE
- Publication number 20210109883
- Publication date Apr 15, 2021
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERIPHERY SHORELINE AUGMENTATION FOR INTEGRATED CIRCUITS
- Publication number 20210072908
- Publication date Mar 11, 2021
- Intel Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERIPHERY SHORELINE AUGMENTATION FOR INTEGRATED CIRCUITS
- Publication number 20200104064
- Publication date Apr 2, 2020
- Intel Corporation
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Serial Memory Interface Circuitry for Programmable Integrated Circuits
- Publication number 20200059318
- Publication date Feb 20, 2020
- Altera Corporation
- Jeffrey Schulz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SEEMINGLY MONOLITHIC INTERFACE BETWEEN SEPARATE INTEGRATED CIRCUIT DIE
- Publication number 20200028521
- Publication date Jan 23, 2020
- Intel Corporation
- David W. Mendel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE
- Publication number 20190361831
- Publication date Nov 28, 2019
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION...
- Publication number 20190018063
- Publication date Jan 17, 2019
- Altera Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEEMINGLY MONOLITHIC INTERFACE BETWEEN SEPARATE INTEGRATED CIRCUIT DIE
- Publication number 20180183463
- Publication date Jun 28, 2018
- Intel Corporation
- David W. Mendel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE
- Publication number 20180181524
- Publication date Jun 28, 2018
- Intel Corporation
- Jeffrey Erik Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SERIAL MEMORY INTERFACE CIRCUITRY FOR PROGRAMMABLE INTEGRATED CIRCUITS
- Publication number 20170310340
- Publication date Oct 26, 2017
- Altera Corporation
- Jeffrey Schulz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MIXED REDUNDANCY SCHEME FOR INTER-DIE INTERCONNECTS IN A MULTICHIP...
- Publication number 20160363626
- Publication date Dec 15, 2016
- Altera Corporation
- Dana How
- G01 - MEASURING TESTING
Information Patent Application
Method And Circuit For Scalable Cross Point Switching Using 3-D Die...
- Publication number 20150341037
- Publication date Nov 26, 2015
- Altera Corporation
- Jeffrey Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLERS WITH DYNAMIC PORT PRIORITY ASSIGNMENT CAPABILITIES
- Publication number 20120311277
- Publication date Dec 6, 2012
- Michael H.M. Chu
- G06 - COMPUTING CALCULATING COUNTING

Jeffrey Schulz

Person

Patents Grantslast 30 patents

Seemingly monolithic interface between separate integrated circuit die

Interface bridge between integrated circuit die

Interface bridge between integrated circuit die

Periphery shoreline augmentation for integrated circuits

Interface bridge between integrated circuit die

Serial memory interface circuitry for programmable integrated circuits

Interface bridge between integrated circuit die

Seemingly monolithic interface between separate integrated circuit die

Periphery shoreline augmentation for integrated circuits

Programmable integrated circuits with in-operation reconfiguration...

Serial memory interface circuitry for programmable integrated circuits

Interface bridge between integrated circuit die

Seemingly monolithic interface between separate integrated circuit die

Mixed redundancy scheme for inter-die interconnects in a multichip...

Mixed redundancy scheme for inter-die interconnects in a multichip...

Method and apparatuses for optimizing power management on an integr...

Serial memory interface circuitry for programmable integrated circuits

Integrated circuit with bonding circuits for bonding memory control...

Transaction handling between soft logic and hard logic components o...

Method and system for operating a multi-port memory system

Method and circuit for scalable cross point switching using 3-D die...

Memory controller interface with adjustable port widths

Memory controllers with dynamic port priority assignment capabilities

Method and circuit for scalable cross point switching using 3-D die...

Systems and methods for providing memory controllers with memory ac...

Systems and methods for providing memory controllers with scheduler...

Patents Applicationslast 30 patents

Double Bump Design for Multiple Purpose IO Connections

Interface Bridge Between Integrated Circuit Die

INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE

Input Output Banks of a Programmable Logic Device

Source Synchronous Partition of an SDRAM Controller Subsystem

Techniques For Synchronous Accesses To Storage Circuits

SYSTEMS AND METHODS FOR REDUCING CONGESTION ON NETWORK-ON-CHIP

SEEMINGLY MONOLITHIC INTERFACE BETWEEN SEPARATE INTEGRATED CIRCUIT DIE

INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE

INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE

PERIPHERY SHORELINE AUGMENTATION FOR INTEGRATED CIRCUITS

PERIPHERY SHORELINE AUGMENTATION FOR INTEGRATED CIRCUITS

Serial Memory Interface Circuitry for Programmable Integrated Circuits

SEEMINGLY MONOLITHIC INTERFACE BETWEEN SEPARATE INTEGRATED CIRCUIT DIE

INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE

PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION...

SEEMINGLY MONOLITHIC INTERFACE BETWEEN SEPARATE INTEGRATED CIRCUIT DIE

INTERFACE BRIDGE BETWEEN INTEGRATED CIRCUIT DIE

SERIAL MEMORY INTERFACE CIRCUITRY FOR PROGRAMMABLE INTEGRATED CIRCUITS

MIXED REDUNDANCY SCHEME FOR INTER-DIE INTERCONNECTS IN A MULTICHIP...

Method And Circuit For Scalable Cross Point Switching Using 3-D Die...

MEMORY CONTROLLERS WITH DYNAMIC PORT PRIORITY ASSIGNMENT CAPABILITIES