Jens Graf

Person

Gochsheim, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Arrangement comprising a first semiconductor chip and a second semi...
- Patent number 8,380,899
- Issue date Feb 19, 2013
- Infineon Technologies AG
- Jens Barrenscheen
- G05 - CONTROLLING REGULATING
Information Patent Grant
Arrangement comprising a first semiconductor chip and a second semi...
- Patent number 8,112,563
- Issue date Feb 7, 2012
- Infineon Technologies AG
- Jens Barrenscheen
- G05 - CONTROLLING REGULATING
Information Patent Grant
Arrangement comprising a first semiconductor chip and a second semi...
- Patent number 7,738,588
- Issue date Jun 15, 2010
- Infineon Technologies AG
- Jens Barrenscheen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory arrangement and method for reading from a memory arrangement
- Patent number 7,418,566
- Issue date Aug 26, 2008
- Robert Bosch GmbH
- Jens Graf
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Set of peripheral chips
- Patent number 7,079,934
- Issue date Jul 18, 2006
- Robert Bosch GmbH
- Jens Graf
- G05 - CONTROLLING REGULATING
Information Patent Grant
Device having a memory element, and a memory element
- Patent number 6,765,829
- Issue date Jul 20, 2004
- Robert Bosch GmbH
- Jens Graf
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device and method for controlling operational sequences, in particu...
- Patent number 6,650,976
- Issue date Nov 18, 2003
- Robert Bosch GmbH
- Horst Wagner
- G05 - CONTROLLING REGULATING

Patents Applicationslast 30 patents

Information Patent Application
ARRANGEMENT COMPRISING A FIRST SEMICONDUCTOR CHIP AND A SECOND SEMI...
- Publication number 20120117283
- Publication date May 10, 2012
- Robert Bosch GmbH
- Jens Barrenscheen
- G05 - CONTROLLING REGULATING
Information Patent Application
Set of peripheral chips
- Publication number 20040249551
- Publication date Dec 9, 2004
- Jens Graf
- G05 - CONTROLLING REGULATING
Information Patent Application
Arrangement comprising a first semiconductor chip and a second semi...
- Publication number 20040232449
- Publication date Nov 25, 2004
- Infineon Technologies AG
- Jens Barrenscheen
- G05 - CONTROLLING REGULATING
Information Patent Application
Arrangement comprising a first semiconductor chip and a second semi...
- Publication number 20040225418
- Publication date Nov 11, 2004
- Infineon Technologies AG
- Jens Barrenscheen
- G05 - CONTROLLING REGULATING
Information Patent Application
Memory arrangement and method for reading from a memory arrangement
- Publication number 20020144051
- Publication date Oct 3, 2002
- Jens Graf
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Device having a memory element, and a memory element
- Publication number 20020126542
- Publication date Sep 12, 2002
- Jens Graf
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Device and method for controlling operational sequences, in particu...
- Publication number 20020080026
- Publication date Jun 27, 2002
- Horst Wagner
- G05 - CONTROLLING REGULATING

Person

Patents Grantslast 30 patents

Arrangement comprising a first semiconductor chip and a second semi...

Arrangement comprising a first semiconductor chip and a second semi...

Arrangement comprising a first semiconductor chip and a second semi...

Memory arrangement and method for reading from a memory arrangement

Set of peripheral chips

Device having a memory element, and a memory element

Device and method for controlling operational sequences, in particu...

Patents Applicationslast 30 patents

ARRANGEMENT COMPRISING A FIRST SEMICONDUCTOR CHIP AND A SECOND SEMI...

Set of peripheral chips

Arrangement comprising a first semiconductor chip and a second semi...

Arrangement comprising a first semiconductor chip and a second semi...

Memory arrangement and method for reading from a memory arrangement

Device having a memory element, and a memory element

Device and method for controlling operational sequences, in particu...