Jens Noack

Person

Stuttgart, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Layouting of interconnect lines in integrated circuits
- Patent number 10,579,773
- Issue date Mar 3, 2020
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layouting of interconnect lines in integrated circuits
- Patent number 10,417,377
- Issue date Sep 17, 2019
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Activation of memory core circuits in an integrated circuit
- Patent number 10,388,357
- Issue date Aug 20, 2019
- International Business Machines Corporation
- Thomas Kalla
- G11 - INFORMATION STORAGE
Information Patent Grant
Activation of memory core circuits in an integrated circuit
- Patent number 10,210,923
- Issue date Feb 19, 2019
- International Business Machines Corporation
- Thomas Kalla
- G11 - INFORMATION STORAGE
Information Patent Grant
Activation of memory core circuits in an integrated circuit
- Patent number 10,204,674
- Issue date Feb 12, 2019
- International Business Machines Corporation
- Thomas Kalla
- G11 - INFORMATION STORAGE
Information Patent Grant
Layouting of interconnect lines in integrated circuits
- Patent number 10,013,521
- Issue date Jul 3, 2018
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling an incremental sign-off process using design data
- Patent number 9,922,154
- Issue date Mar 20, 2018
- International Business Machines Corporation
- Hans-Werner Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
NAND-based write driver for SRAM
- Patent number 9,837,143
- Issue date Dec 5, 2017
- International Business Machines Corporation
- Hans-Werner Anderson
- G11 - INFORMATION STORAGE
Information Patent Grant
Write-bitline control in multicore SRAM arrays
- Patent number 9,761,304
- Issue date Sep 12, 2017
- International Business Machines Corporation
- Joachim Keinert
- G11 - INFORMATION STORAGE
Information Patent Grant
Parsing data representative of a hardware design into commands of a...
- Patent number 8,756,538
- Issue date Jun 17, 2014
- International Business Machines Corporation
- Hans-Werner Anderson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT
- Publication number 20190228811
- Publication date Jul 25, 2019
- International Business Machines Corporation
- Thomas Kalla
- G11 - INFORMATION STORAGE
Information Patent Application
ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT
- Publication number 20190019549
- Publication date Jan 17, 2019
- International Business Machines Corporation
- Thomas Kalla
- G11 - INFORMATION STORAGE
Information Patent Application
ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT
- Publication number 20190019547
- Publication date Jan 17, 2019
- International Business Machines Corporation
- Thomas Kalla
- G11 - INFORMATION STORAGE
Information Patent Application
ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT
- Publication number 20190019548
- Publication date Jan 17, 2019
- International Business Machines Corporation
- Thomas Kalla
- G11 - INFORMATION STORAGE
Information Patent Application
LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS
- Publication number 20180285514
- Publication date Oct 4, 2018
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS
- Publication number 20180285513
- Publication date Oct 4, 2018
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING AN INCREMENTAL SIGN-OFF PROCESS USING DESIGN DATA
- Publication number 20170337314
- Publication date Nov 23, 2017
- International Business Machines Corporation
- Hans-Werner Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS
- Publication number 20170140088
- Publication date May 18, 2017
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parsing Data Representative of a Hardware Design into Commands of a...
- Publication number 20130219150
- Publication date Aug 22, 2013
- International Business Machines Corporation
- Hans-Werner Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC ADDITION OF POWER CONNECTIONS TO CHIP POWER
- Publication number 20060085778
- Publication date Apr 20, 2006
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Layouting of interconnect lines in integrated circuits

Layouting of interconnect lines in integrated circuits

Activation of memory core circuits in an integrated circuit

Activation of memory core circuits in an integrated circuit

Activation of memory core circuits in an integrated circuit

Layouting of interconnect lines in integrated circuits

Enabling an incremental sign-off process using design data

NAND-based write driver for SRAM

Write-bitline control in multicore SRAM arrays

Parsing data representative of a hardware design into commands of a...

Patents Applicationslast 30 patents

ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT

ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT

ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT

ACTIVATION OF MEMORY CORE CIRCUITS IN AN INTEGRATED CIRCUIT

LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS

LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS

ENABLING AN INCREMENTAL SIGN-OFF PROCESS USING DESIGN DATA

LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS

Parsing Data Representative of a Hardware Design into Commands of a...

AUTOMATIC ADDITION OF POWER CONNECTIONS TO CHIP POWER