Jeremy A. Wahl

Person

Delmar, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Interconnect structures with airgaps and dielectric-capped intercon...
- Patent number 10,707,119
- Issue date Jul 7, 2020
- GLOBALFOUNDRIES Inc.
- Nicholas V. LiCausi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including a leveling dielectric fill material
- Patent number 10,395,981
- Issue date Aug 27, 2019
- GLOBALFOUNDRIES Inc.
- Hans-Peter Moll
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing selective nanostructures into finFET proces...
- Patent number 10,049,944
- Issue date Aug 14, 2018
- GLOBALFOUNDRIES Inc.
- Scott Beasor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Spacer defined fin growth and differential fin width
- Patent number 9,875,936
- Issue date Jan 23, 2018
- GLOBALFOUNDRIES Inc.
- Ryan Sporer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits with dual silicide contacts and methods for fab...
- Patent number 9,660,075
- Issue date May 23, 2017
- GLOBALFOUNDRIES, INC.
- Shao Ming Koh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming FinFET devices with substantially undoped channe...
- Patent number 9,634,143
- Issue date Apr 25, 2017
- GLOBALFOUNDRIES Inc.
- Jeremy A. Wahl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to protect MOL metallization from hardmask strip process
- Patent number 9,570,344
- Issue date Feb 14, 2017
- GLOBALFOUNDRIES Inc.
- Vimal Kamineni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with a multiple nanowire channel structure and...
- Patent number 9,508,712
- Issue date Nov 29, 2016
- GLOBALFOUNDRIES Inc.
- Jeremy Austin Wahl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits with dual silicide contacts and methods for fab...
- Patent number 9,293,462
- Issue date Mar 22, 2016
- GLOBALFOUNDRIES, INC.
- Shao Ming Koh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits with dual silicide contacts and methods for fab...
- Patent number 9,196,694
- Issue date Nov 24, 2015
- GLOBALFOUNDRIES, INC.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits with metal-insulator-semiconductor (MIS) contac...
- Patent number 9,177,805
- Issue date Nov 3, 2015
- GLOBALFOUNDRIES, INC.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming a masking layer for patterning underlying struct...
- Patent number 8,969,207
- Issue date Mar 3, 2015
- GLOBALFOUNDRIES Inc.
- Gerard M. Schmid
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained silicon carbide channel for electron mobility of NMOS
- Patent number 8,963,255
- Issue date Feb 24, 2015
- GLOBALFOUNDRIES Inc.
- Jeremy A. Wahl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming trench/via features in an underlying structure u...
- Patent number 8,906,802
- Issue date Dec 9, 2014
- GLOBALFOUNDRIES Inc.
- Jeremy A. Wahl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming a semiconductor device with a nanowire channel s...
- Patent number 8,853,019
- Issue date Oct 7, 2014
- GLOBALFOUNDRIES Inc.
- Jody A. Fronheiser
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Methods of trimming nanowire structures
- Patent number 8,846,511
- Issue date Sep 30, 2014
- GLOBALFOUNDRIES Inc.
- Nicholas V. LiCausi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic device having plural FIN-FETs with different FIN heights...
- Patent number 8,759,904
- Issue date Jun 24, 2014
- GLOBALFOUNDRIES, INC.
- Jeremy A. Wahl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained silicon carbide channel for electron mobility of NMOS
- Patent number 8,722,482
- Issue date May 13, 2014
- GLOBALFOUNDRIES Inc.
- Jeremy A. Wahl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming dielectrically isolated fins for a FinFET semico...
- Patent number 8,691,640
- Issue date Apr 8, 2014
- GLOBALFOUNDRIES Inc.
- Nicholas V. LiCausi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of epitaxial FinFET
- Patent number 8,481,410
- Issue date Jul 9, 2013
- GLOBALFOUNDRIES Inc.
- Nicholas LiCausi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of FinFET height control
- Patent number 8,476,137
- Issue date Jul 2, 2013
- GLOBALFOUNDRIES Inc.
- Nicholas LiCausi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FIN-FET device and method and integrated circuits using such
- Patent number 8,460,984
- Issue date Jun 11, 2013
- GLOBALFOUNDRIES, INC.
- Jeremy Wahl
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTERCONNECT STRUCTURES WITH AIRGAPS AND DIELECTRIC-CAPPED INTERCON...
- Publication number 20200227308
- Publication date Jul 16, 2020
- GLOBALFOUNDRIES INC.
- Nicholas V. LiCausi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING A LEVELING DIELECTRIC FILL MATERIAL
- Publication number 20190122921
- Publication date Apr 25, 2019
- GLOBALFOUNDRIES INC.
- Hans-Peter Moll
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPACER DEFINED FIN GROWTH AND DIFFERENTIAL FIN WIDTH
- Publication number 20180130712
- Publication date May 10, 2018
- GLOBALFOUNDRIES INC.
- Ryan SPORER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MANUFACTURING SELECTIVE NANOSTRUCTURES INTO FINFET PROCES...
- Publication number 20180096899
- Publication date Apr 5, 2018
- GLOBALFOUNDRIES INC.
- Scott BEASOR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO PROTECT MOL METALLIZATION FROM HARDMASK STRIP PROCESS
- Publication number 20160379872
- Publication date Dec 29, 2016
- GLOBALFOUNDRIES INC.
- Vimal KAMINENI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING SEMICONDUCTOR STRUCTURE WITH CONDENSED SILI...
- Publication number 20160254145
- Publication date Sep 1, 2016
- GLOBALFOUNDRIES INC.
- Dina H. TRIYOSO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FAB...
- Publication number 20160172493
- Publication date Jun 16, 2016
- GLOBALFOUNDRIES, Inc.
- Shao Ming Koh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FAB...
- Publication number 20160049490
- Publication date Feb 18, 2016
- GLOBALFOUNDRIES, Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IINTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FA...
- Publication number 20150214228
- Publication date Jul 30, 2015
- GLOBALFOUNDRIES, Inc.
- Shao Ming Koh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUITS WITH METAL-INSULATOR-SEMICONDUCTOR (MIS) CONTAC...
- Publication number 20150214059
- Publication date Jul 30, 2015
- GLOBALFOUNDRIES, Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH A MULTIPLE NANOWIRE CHANNEL STRUCTURE AND...
- Publication number 20150187762
- Publication date Jul 2, 2015
- GLOBALFOUNDRIES INC.
- Jeremy Austin Wahl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FAB...
- Publication number 20150091093
- Publication date Apr 2, 2015
- GLOBAL FOUNDRIES, INC.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING TRENCH/VIA FEATURES IN AN UNDERLYING STRUCTURE U...
- Publication number 20140273469
- Publication date Sep 18, 2014
- Jeremy A. Wahl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING A MASKING LAYER FOR PATTERNING UNDERLYING STRUCT...
- Publication number 20140273473
- Publication date Sep 18, 2014
- GLOBALFOUNDRIES INC.
- Gerard M. Schmid
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A NANOWIRE CHANNEL S...
- Publication number 20140273423
- Publication date Sep 18, 2014
- GLOBALFOUNDRIES INC.
- Jody A. Fronheiser
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHODS OF TRIMMING NANOWIRE STRUCTURES
- Publication number 20140227849
- Publication date Aug 14, 2014
- GLOBALFOUNDRIES INC.
- Nicholas V. LiCausi
- B82 - NANO-TECHNOLOGY
Information Patent Application
STRAINED SILICON CARBIDE CHANNEL FOR ELECTRON MOBILITY OF NMOS
- Publication number 20140203298
- Publication date Jul 24, 2014
- GLOBALFOUNDRIES INC.
- Jeremy A. WAHL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF EPITAXIAL FINFET
- Publication number 20130196485
- Publication date Aug 1, 2013
- GLOBALFOUNDRIES INC.
- Nicholas LiCausi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMBINED PLANAR FET AND FIN-FET DEVICES AND METHODS
- Publication number 20130049136
- Publication date Feb 28, 2013
- Jeremy A. Wahl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN-FET DEVICE AND METHOD AND INTEGRATED CIRCUITS USING SUCH
- Publication number 20120313169
- Publication date Dec 13, 2012
- GLOBALFOUNDRIES INC.
- Jeremy Wahl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED SILICON CARBIDE CHANNEL FOR ELECTRON MOBILITY OF NMOS
- Publication number 20110227094
- Publication date Sep 22, 2011
- GLOBALFOUNDRIES INC.
- Jeremy A. Wahl
- H01 - BASIC ELECTRIC ELEMENTS

Jeremy A. Wahl

Person

Patents Grantslast 30 patents

Interconnect structures with airgaps and dielectric-capped intercon...

Semiconductor device including a leveling dielectric fill material

Method of manufacturing selective nanostructures into finFET proces...

Spacer defined fin growth and differential fin width

Integrated circuits with dual silicide contacts and methods for fab...

Methods of forming FinFET devices with substantially undoped channe...

Method to protect MOL metallization from hardmask strip process

Semiconductor device with a multiple nanowire channel structure and...

Integrated circuits with dual silicide contacts and methods for fab...

Integrated circuits with dual silicide contacts and methods for fab...

Integrated circuits with metal-insulator-semiconductor (MIS) contac...

Methods of forming a masking layer for patterning underlying struct...

Strained silicon carbide channel for electron mobility of NMOS

Methods of forming trench/via features in an underlying structure u...

Methods of forming a semiconductor device with a nanowire channel s...

Methods of trimming nanowire structures

Electronic device having plural FIN-FETs with different FIN heights...

Strained silicon carbide channel for electron mobility of NMOS

Methods of forming dielectrically isolated fins for a FinFET semico...

Methods of epitaxial FinFET

Methods of FinFET height control

FIN-FET device and method and integrated circuits using such

Patents Applicationslast 30 patents

INTERCONNECT STRUCTURES WITH AIRGAPS AND DIELECTRIC-CAPPED INTERCON...

SEMICONDUCTOR DEVICE INCLUDING A LEVELING DIELECTRIC FILL MATERIAL

SPACER DEFINED FIN GROWTH AND DIFFERENTIAL FIN WIDTH

METHOD OF MANUFACTURING SELECTIVE NANOSTRUCTURES INTO FINFET PROCES...

METHOD TO PROTECT MOL METALLIZATION FROM HARDMASK STRIP PROCESS

METHODS FOR FABRICATING SEMICONDUCTOR STRUCTURE WITH CONDENSED SILI...

INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FAB...

INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FAB...

IINTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FA...

INTEGRATED CIRCUITS WITH METAL-INSULATOR-SEMICONDUCTOR (MIS) CONTAC...

SEMICONDUCTOR DEVICE WITH A MULTIPLE NANOWIRE CHANNEL STRUCTURE AND...

INTEGRATED CIRCUITS WITH DUAL SILICIDE CONTACTS AND METHODS FOR FAB...

METHODS OF FORMING TRENCH/VIA FEATURES IN AN UNDERLYING STRUCTURE U...

METHODS OF FORMING A MASKING LAYER FOR PATTERNING UNDERLYING STRUCT...

METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A NANOWIRE CHANNEL S...

METHODS OF TRIMMING NANOWIRE STRUCTURES

STRAINED SILICON CARBIDE CHANNEL FOR ELECTRON MOBILITY OF NMOS

METHODS OF EPITAXIAL FINFET

COMBINED PLANAR FET AND FIN-FET DEVICES AND METHODS

FIN-FET DEVICE AND METHOD AND INTEGRATED CIRCUITS USING SUCH

STRAINED SILICON CARBIDE CHANNEL FOR ELECTRON MOBILITY OF NMOS