Jeremy Rutledge Levitt

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Measure of analysis performed in property checking
- Patent number 9,684,760
- Issue date Jun 20, 2017
- Mentor Graphics Corporation
- Jeremy Rutledge Levitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Measure of analysis performed in property checking
- Patent number 9,262,557
- Issue date Feb 16, 2016
- Mentor Graphics Corporation
- Jeremy Rutledge Levitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Measure of analysis performed in property checking
- Patent number 8,418,121
- Issue date Apr 9, 2013
- Mentor Graphics Corporation
- Jeremy Rutledge Levitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock model for formal verification of a digital circuit description
- Patent number 8,060,847
- Issue date Nov 15, 2011
- Mentor Graphics Corporation
- James Andrew Garrard Seawright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Measure of analysis performed in property checking
- Patent number 7,890,897
- Issue date Feb 15, 2011
- Mentor Graphics Corporation
- Jeremy Rutledge Levitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock model for formal verification of a digital circuit description
- Patent number 7,487,483
- Issue date Feb 3, 2009
- James Andrew Garrard Seawright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selection of initial states for formal verification
- Patent number 7,454,324
- Issue date Nov 18, 2008
- James Andrew Garrard Seawright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Measure of analysis performed in property checking
- Patent number 7,318,205
- Issue date Jan 8, 2008
- Jeremy Rutledge Levitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Measure of analysis performed in property checking
- Patent number 6,848,088
- Issue date Jan 25, 2005
- Mentor Graphics Corporation
- Jeremy Rutledge Levitt
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING
- Publication number 20160125122
- Publication date May 5, 2016
- Mentor Graphics Corporation
- Jeremy Rutledge Levitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING
- Publication number 20130239084
- Publication date Sep 12, 2013
- Mentor Graphics Corporation
- Jeremy Rutledge Levitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING
- Publication number 20110138346
- Publication date Jun 9, 2011
- Mentor Graphics Corporation
- Jeremy Rutledge Levitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK MODEL FOR FORMAL VERIFICATION OF A DIGITAL CIRCUIT DESCRIPTION
- Publication number 20090144684
- Publication date Jun 4, 2009
- Mentor Graphics Corp.
- James Andrew Garrard Seawright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING
- Publication number 20080066032
- Publication date Mar 13, 2008
- Mentor Graphics Corporation
- Jeremy Rutledge Levitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reuse of learned information to simplify functional verification of...
- Publication number 20070299648
- Publication date Dec 27, 2007
- Jeremy R. Levitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock model for formal verification of a digital circuit description
- Publication number 20070271536
- Publication date Nov 22, 2007
- Mentor Graphics Corp.
- James Andrew Garrard Seawright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Measure of analysis performed in property checking
- Publication number 20050081169
- Publication date Apr 14, 2005
- Jeremy Rutledge Levitt
- G06 - COMPUTING CALCULATING COUNTING

Jeremy Rutledge Levitt

Person

Patents Grantslast 30 patents

Measure of analysis performed in property checking

Measure of analysis performed in property checking

Measure of analysis performed in property checking

Clock model for formal verification of a digital circuit description

Measure of analysis performed in property checking

Clock model for formal verification of a digital circuit description

Selection of initial states for formal verification

Measure of analysis performed in property checking

Measure of analysis performed in property checking

Patents Applicationslast 30 patents

MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING

MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING

MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING

CLOCK MODEL FOR FORMAL VERIFICATION OF A DIGITAL CIRCUIT DESCRIPTION

MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING

Reuse of learned information to simplify functional verification of...

Clock model for formal verification of a digital circuit description

Measure of analysis performed in property checking