Jerome J. Johnson

Person

Spring, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Variable channel multi-controller memory system
- Patent number 10,956,342
- Issue date Mar 23, 2021
- Cadence Design Systems, Inc.
- John MacLaren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for memory control having selectively distributed...
- Patent number 10,719,058
- Issue date Jul 21, 2020
- Cadence Design Systems, Inc.
- Jerome J. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for memory control having adaptively split addres...
- Patent number 10,275,306
- Issue date Apr 30, 2019
- Cadence Design Systems, Inc.
- John MacLaren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory testing
- Patent number 7,353,328
- Issue date Apr 1, 2008
- Hewlett-Packard Development Company, L.P.
- John MacLaren
- G11 - INFORMATION STORAGE
Information Patent Grant
Error indication in a raid memory system
- Patent number 7,320,086
- Issue date Jan 15, 2008
- Hewlett-Packard Development Company, L.P.
- Tim Majni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory latency and bandwidth optimizations
- Patent number 7,194,577
- Issue date Mar 20, 2007
- Hewlett-Packard Development Company, L.P.
- Jerome J. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error indication in a raid memory system
- Patent number 7,028,213
- Issue date Apr 11, 2006
- Hewlett-Packard Development Company, L.P.
- Tim Majni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for supporting multi-level striping of non-homogeneous memor...
- Patent number 7,010,652
- Issue date Mar 7, 2006
- Hewlett-Packard Development Company, L.P.
- Gary J. Piccirillo
- G11 - INFORMATION STORAGE
Information Patent Grant
Hot replace power control sequence logic
- Patent number 6,981,095
- Issue date Dec 27, 2005
- Hewlett-Packard Development Company, L.P.
- John M. MacLaren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory latency and bandwidth optimizations
- Patent number 6,938,133
- Issue date Aug 30, 2005
- Hewlett-Packard Development Company, L.P.
- Jerome J. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module resync
- Patent number 6,892,271
- Issue date May 10, 2005
- Hewlett-Packard Development Company, L.P.
- Gary J. Piccirillo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hot-upgrade/hot-add memory
- Patent number 6,854,070
- Issue date Feb 8, 2005
- Hewlett-Packard Development Company, L.P.
- Jerome J. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory auto-precharge
- Patent number 6,832,286
- Issue date Dec 14, 2004
- Hewlett-Packard Development Company, L.P.
- Jerome J. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Real-time hardware memory scrubbing
- Patent number 6,832,340
- Issue date Dec 14, 2004
- Hewlett-Packard Development Company, L.P.
- John E. Larson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for supporting multi-level stripping of non-homogeneous memo...
- Patent number 6,785,785
- Issue date Aug 31, 2004
- Hewlett-Packard Development Company, L.P.
- Gary J. Piccirillo
- G11 - INFORMATION STORAGE
Information Patent Grant
Raid memory
- Patent number 6,785,835
- Issue date Aug 31, 2004
- Hewlett-Packard Development Company, L.P.
- John M. MacLaren
- G11 - INFORMATION STORAGE
Information Patent Grant
Hot-replace of memory
- Patent number 6,766,469
- Issue date Jul 20, 2004
- Hewlett-Packard Development Company, L.P.
- John E. Larson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module resync
- Patent number 6,684,292
- Issue date Jan 27, 2004
- Hewlett-Packard Development Company, L.P.
- Gary J. Piccirillo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hot replace power control sequence logic
- Patent number 6,640,282
- Issue date Oct 28, 2003
- Hewlett-Packard Development Company, L.P.
- John M. MacLaren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with adaptive memory arbitration scheme
- Patent number 6,505,260
- Issue date Jan 7, 2003
- Compaq Information Technologies Group, L.P.
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for concurrently requesting input/output and memo...
- Patent number 6,356,972
- Issue date Mar 12, 2002
- Compaq Information Technologies Group, L.P.
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with adaptive memory arbitration scheme
- Patent number 6,286,083
- Issue date Sep 4, 2001
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with improved memory access
- Patent number 6,279,065
- Issue date Aug 21, 2001
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for improving processor read latency in a system...
- Patent number 6,272,651
- Issue date Aug 7, 2001
- Compaq Computer Corp.
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system employing memory controller and bridge interface pe...
- Patent number 6,247,102
- Issue date Jun 12, 2001
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for optimally deferring or retrying a cycle upon...
- Patent number 6,216,190
- Issue date Apr 10, 2001
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for suppressing processor cycles to memory until...
- Patent number 6,209,052
- Issue date Mar 27, 2001
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for concurrently requesting input/output and memo...
- Patent number 6,202,101
- Issue date Mar 13, 2001
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for aligning an initial cache line of data read f...
- Patent number 6,199,118
- Issue date Mar 6, 2001
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for aligning an initial cache line of data read f...
- Patent number 6,160,562
- Issue date Dec 12, 2000
- Compaq Computer Corporation
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Error indication in a raid memory system
- Publication number 20060085671
- Publication date Apr 20, 2006
- Tim Majni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory testing
- Publication number 20050223265
- Publication date Oct 6, 2005
- John MacLaren
- G11 - INFORMATION STORAGE
Information Patent Application
Memory latency and bandwidth optimizations
- Publication number 20050193166
- Publication date Sep 1, 2005
- Jerome J. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for supporting multi-level striping of non-homogeneous memor...
- Publication number 20050027951
- Publication date Feb 3, 2005
- Gary J. Piccirillo
- G11 - INFORMATION STORAGE
Information Patent Application
Memory module resync
- Publication number 20040088486
- Publication date May 6, 2004
- Gary J. Piccirillo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory latency and bandwidth optimizations
- Publication number 20040073767
- Publication date Apr 15, 2004
- Jerome J. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory auto-precharge
- Publication number 20030236959
- Publication date Dec 25, 2003
- Jerome J. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory module resync
- Publication number 20030101314
- Publication date May 29, 2003
- Gary J. Piccirillo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error indication in a raid memory system
- Publication number 20030088805
- Publication date May 8, 2003
- Tim Majni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory latency and bandwidth optimizations
- Publication number 20030070055
- Publication date Apr 10, 2003
- Jerome J. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for supporting multi-level stripping of non-homogeneous memo...
- Publication number 20020053010
- Publication date May 2, 2002
- Gary J. Piccirillo
- G11 - INFORMATION STORAGE
Information Patent Application
Hot-replace of memory
- Publication number 20020042893
- Publication date Apr 11, 2002
- John E. Larson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hot-upgrade/hot-add memory
- Publication number 20020010875
- Publication date Jan 24, 2002
- Jerome J. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hot replace power control sequence logic
- Publication number 20020002651
- Publication date Jan 3, 2002
- John M. MacLaren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Real-time hardware memory scrubbing
- Publication number 20010047497
- Publication date Nov 29, 2001
- John E. Larson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Raid memory
- Publication number 20010039632
- Publication date Nov 8, 2001
- John M. MacLaren
- G11 - INFORMATION STORAGE
Information Patent Application
Computer system with adaptive memory arbitration scheme
- Publication number 20010010066
- Publication date Jul 26, 2001
- Kenneth T. Chin
- G06 - COMPUTING CALCULATING COUNTING

Jerome J. Johnson

Person

Patents Grantslast 30 patents

Variable channel multi-controller memory system

System and method for memory control having selectively distributed...

System and method for memory control having adaptively split addres...

Memory testing

Error indication in a raid memory system

Memory latency and bandwidth optimizations

Error indication in a raid memory system

Method for supporting multi-level striping of non-homogeneous memor...

Hot replace power control sequence logic

Memory latency and bandwidth optimizations

Memory module resync

Hot-upgrade/hot-add memory

Memory auto-precharge

Real-time hardware memory scrubbing

Method for supporting multi-level stripping of non-homogeneous memo...

Raid memory

Hot-replace of memory

Memory module resync

Hot replace power control sequence logic

Computer system with adaptive memory arbitration scheme

System and method for concurrently requesting input/output and memo...

Computer system with adaptive memory arbitration scheme

Computer system with improved memory access

System and method for improving processor read latency in a system...

Computer system employing memory controller and bridge interface pe...

System and method for optimally deferring or retrying a cycle upon...

System and method for suppressing processor cycles to memory until...

System and method for concurrently requesting input/output and memo...

System and method for aligning an initial cache line of data read f...

System and method for aligning an initial cache line of data read f...

Patents Applicationslast 30 patents

Error indication in a raid memory system

Memory testing

Memory latency and bandwidth optimizations

Method for supporting multi-level striping of non-homogeneous memor...

Memory module resync

Memory latency and bandwidth optimizations

Memory auto-precharge

Memory module resync

Error indication in a raid memory system

Memory latency and bandwidth optimizations

Method for supporting multi-level stripping of non-homogeneous memo...

Hot-replace of memory

Hot-upgrade/hot-add memory

Hot replace power control sequence logic

Real-time hardware memory scrubbing

Raid memory

Computer system with adaptive memory arbitration scheme