Jerome Vincent Coffin

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for high-speed data bus connection and fabric...
- Patent number 11,593,291
- Issue date Feb 28, 2023
- GigaIO Networks, Inc.
- Eric Pilmore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disjointed virtual memory scheme with block bypass
- Patent number 10,380,027
- Issue date Aug 13, 2019
- FRIDAY HARBOR LLC
- Jerome Vincent Coffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet router buffer management
- Patent number 10,331,569
- Issue date Jun 25, 2019
- FRIDAY HARBOR LLC
- Michael Florea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Affinity data collection in a computing system
- Patent number 10,108,516
- Issue date Oct 23, 2018
- KnuEdge Incorporated
- Douglas A. Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DMA engine for transferring data in a network-on-a-chip processor
- Patent number 10,078,606
- Issue date Sep 18, 2018
- KNUEDGE, INC.
- Douglas A. Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chained packet sequences in a network on a chip architecture
- Patent number 10,027,583
- Issue date Jul 17, 2018
- KnuEdge Incorporated
- Andrew White
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flow control through packet router
- Patent number 9,977,745
- Issue date May 22, 2018
- KNUEDGE, INC.
- Michael Florea
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory-attached computing resource in network on a chip architectur...
- Patent number 9,959,066
- Issue date May 1, 2018
- KnuEdge Incorporated
- Douglas A. Palmer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Router path selection and creation in a single clock cycle
- Patent number 9,942,146
- Issue date Apr 10, 2018
- KnuEdge Incorporated
- Michael Florea
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Synchronization in a multi-processor computing system
- Patent number 9,910,716
- Issue date Mar 6, 2018
- KnuEdge Incorporated
- Douglas B. Meyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing write operations in a network on a chip device
- Patent number 9,864,519
- Issue date Jan 9, 2018
- KnuEdge Incorporated
- Doug Meyer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Performing read operations in network on a chip architecture
- Patent number 9,686,191
- Issue date Jun 20, 2017
- KnuEdge Incorporation
- Andy White
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Topology discovery in a computing system
- Patent number 9,634,901
- Issue date Apr 25, 2017
- KnuEdge Incorporated
- Douglas A. Palmer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
INTERNET PROTOCOL COMMUNICATIONS OVER ALTERNATIVE FREQUENCY BAND OF...
- Publication number 20240291688
- Publication date Aug 29, 2024
- Fuse Integration, Inc.
- Jerome V. COFFIN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHODS AND APPARATUS FOR HIGH-SPEED DATA BUS CONNECTION AND FABRIC...
- Publication number 20200081858
- Publication date Mar 12, 2020
- GigaIO Networks, Inc.
- Eric Philmore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Router Path Selection and Creation in a Single Clock Cycle
- Publication number 20180041434
- Publication date Feb 8, 2018
- KnuEdge Incorporated
- Michael Florea
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
NETWORK ON CHIP WITH TASK QUEUES
- Publication number 20170351555
- Publication date Dec 7, 2017
- KNUEDGE, INC.
- Jerome Vincent Coffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Chained Packet Sequences in a Network on a Chip Architecture
- Publication number 20170279714
- Publication date Sep 28, 2017
- KnuEdge Incorporated
- Andrew White
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Synchronization in a Multi-Processor Computing System
- Publication number 20170262318
- Publication date Sep 14, 2017
- KnuEdge Incorporated
- Douglas B. Meyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory-Attached Computing Resource in Network on a Chip Architecture
- Publication number 20170235511
- Publication date Aug 17, 2017
- KnuEdge Incorporated
- Douglas A. Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKET ROUTER BUFFER MANAGEMENT
- Publication number 20170195248
- Publication date Jul 6, 2017
- KNUEDGE, INC.
- Michael Florea
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
FLOW CONTROL THROUGH PACKET ROUTER
- Publication number 20170195259
- Publication date Jul 6, 2017
- KNUEDGE, INC.
- Michael Florea
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DISJOINTED VIRTUAL MEMORY SCHEME WITH BLOCK BYPASS
- Publication number 20170192901
- Publication date Jul 6, 2017
- KNUEDGE, INC.
- Jerome Vincent Coffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SMART DMA ENGINE FOR A NETWORK-ON-A-CHIP PROCESSOR
- Publication number 20170153993
- Publication date Jun 1, 2017
- KNUEDGE, INC.
- Douglas A. Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE PROCESSOR ACCESS TO SHARED PROGRAM MEMORY
- Publication number 20170147513
- Publication date May 25, 2017
- KNUEDGE, INC.
- Robert Nicholas Hilton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Affinity Data Collection in a Computing System
- Publication number 20170125073
- Publication date May 4, 2017
- KnuEdge Incorporated
- Douglas A. Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performing Write Operations In A Network On A Chip Device
- Publication number 20170060420
- Publication date Mar 2, 2017
- KnuEdge Incorporated
- Doug Meyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performing Read Operations in Network on a Chip Architecture
- Publication number 20170054635
- Publication date Feb 23, 2017
- Knu Edge Incorporated
- Andy White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Topology Discovery in a Computing System
- Publication number 20160226712
- Publication date Aug 4, 2016
- The Intellisis Corporation
- Douglas A. PALMER
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Jerome Vincent Coffin

Person

Patents Grantslast 30 patents

Methods and apparatus for high-speed data bus connection and fabric...

Disjointed virtual memory scheme with block bypass

Packet router buffer management

Affinity data collection in a computing system

DMA engine for transferring data in a network-on-a-chip processor

Chained packet sequences in a network on a chip architecture

Flow control through packet router

Memory-attached computing resource in network on a chip architectur...

Router path selection and creation in a single clock cycle

Synchronization in a multi-processor computing system

Performing write operations in a network on a chip device

Performing read operations in network on a chip architecture

Topology discovery in a computing system

Patents Applicationslast 30 patents

INTERNET PROTOCOL COMMUNICATIONS OVER ALTERNATIVE FREQUENCY BAND OF...

METHODS AND APPARATUS FOR HIGH-SPEED DATA BUS CONNECTION AND FABRIC...

Router Path Selection and Creation in a Single Clock Cycle

NETWORK ON CHIP WITH TASK QUEUES

Chained Packet Sequences in a Network on a Chip Architecture

Synchronization in a Multi-Processor Computing System

Memory-Attached Computing Resource in Network on a Chip Architecture

PACKET ROUTER BUFFER MANAGEMENT

FLOW CONTROL THROUGH PACKET ROUTER

DISJOINTED VIRTUAL MEMORY SCHEME WITH BLOCK BYPASS

SMART DMA ENGINE FOR A NETWORK-ON-A-CHIP PROCESSOR

MULTIPLE PROCESSOR ACCESS TO SHARED PROGRAM MEMORY

Affinity Data Collection in a Computing System

Performing Write Operations In A Network On A Chip Device

Performing Read Operations in Network on a Chip Architecture

Topology Discovery in a Computing System