Jerry Burch

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Portland, OR, US

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Patents Grantslast 30 patents

Information Patent Grant
Integrating a boolean SAT solver into a router
- Patent number 7,904,867
- Issue date Mar 8, 2011
- Synopsys, Inc.
- Jerry R. Burch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formally proving the functional equivalence of pipelined designs co...
- Patent number 7,836,414
- Issue date Nov 16, 2010
- Synopsys, Inc.
- Alfred Koelbl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formally proving the functional equivalence of pipelined designs co...
- Patent number 7,389,479
- Issue date Jun 17, 2008
- Synopsys, Inc.
- Alfred Koelbl
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Integrating a boolean SAT solver into a router
- Publication number 20080250376
- Publication date Oct 9, 2008
- Jerry R. Burch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FORMALLY PROVING THE FUNCTIONAL EQUIVALENCE OF PIPELINED DESIGNS CO...
- Publication number 20080209370
- Publication date Aug 28, 2008
- Synopsys, Inc.
- Alfred Koelbl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Formally proving the functional equivalence of pipelined designs co...
- Publication number 20070143717
- Publication date Jun 21, 2007
- Alfred Koelbl
- G06 - COMPUTING CALCULATING COUNTING