Jerzy Tyszer

Person

Poznan, PL

People

Patents Grantslast 30 patents

Information Patent Grant
Universal compactor architecture for testing circuits
- Patent number 11,815,555
- Issue date Nov 14, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Grant
Trajectory-optimized test pattern generation for built-in self-test
- Patent number 11,585,853
- Issue date Feb 21, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Grant
Deterministic stellar built-in self test
- Patent number 11,555,854
- Issue date Jan 17, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Grant
Flexible isometric decompressor architecture for test compression
- Patent number 11,150,299
- Issue date Oct 19, 2021
- SIEMENS INDUSTRY SOFTWARE INC.
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test scheduling and test access in test compression environment
- Patent number 10,955,460
- Issue date Mar 23, 2021
- Mentor Graphics Corporation
- Mark Kassab
- G01 - MEASURING TESTING
Information Patent Grant
Test application time reduction using capture-per-cycle test points
- Patent number 10,509,072
- Issue date Dec 17, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test point insertion for low test pattern counts
- Patent number 10,444,282
- Issue date Oct 15, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain stitching for test-per-clock
- Patent number 10,379,161
- Issue date Aug 13, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test point-enhanced hardware security
- Patent number 10,361,873
- Issue date Jul 23, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Continuous application and decompression of test patterns and selec...
- Patent number 10,234,506
- Issue date Mar 19, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Low power testing based on dynamic grouping of scan
- Patent number 10,120,029
- Issue date Nov 6, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Multi-stage test response compactors
- Patent number 10,120,024
- Issue date Nov 6, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Deterministic built-in self-test based on compressed test patterns...
- Patent number 9,933,485
- Issue date Apr 3, 2018
- Mentor Graphics Corporation
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Grant
Multi-stage test response compactors
- Patent number 9,778,316
- Issue date Oct 3, 2017
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Scan-based test architecture for interconnects in stacked designs
- Patent number 9,720,041
- Issue date Aug 1, 2017
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test-per-clock based on dynamically-partitioned reconfigurable scan...
- Patent number 9,714,981
- Issue date Jul 25, 2017
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Continuous application and decompression of test patterns and selec...
- Patent number 9,664,739
- Issue date May 30, 2017
- Mentor Graphics Corporation
- Janusz Rasjki
- G01 - MEASURING TESTING
Information Patent Grant
Isometric test compression with low toggling activity
- Patent number 9,651,622
- Issue date May 16, 2017
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Selective per-cycle masking of scan chains for system level test
- Patent number 9,377,508
- Issue date Jun 28, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test generation for test-per-clock
- Patent number 9,347,993
- Issue date May 24, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test-per-clock based on dynamically-partitioned reconfigurable scan...
- Patent number 9,335,377
- Issue date May 10, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
On-chip comparison and response collection tools and techniques
- Patent number 9,250,287
- Issue date Feb 2, 2016
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G01 - MEASURING TESTING
Information Patent Grant
Continuous application and decompression of test patterns and selec...
- Patent number 9,134,370
- Issue date Sep 15, 2015
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test scheduling with pattern-independent test access mechanism
- Patent number 9,088,522
- Issue date Jul 21, 2015
- Mentor Graphics Corporation
- Janusz Rajski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Scan chain configuration for test-per-clock based on circuit topology
- Patent number 9,009,553
- Issue date Apr 14, 2015
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Fault-driven scan chain configuration for test-per-clock
- Patent number 9,003,248
- Issue date Apr 7, 2015
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
On-chip comparison and response collection tools and techniques
- Patent number 8,914,694
- Issue date Dec 16, 2014
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G01 - MEASURING TESTING
Information Patent Grant
Low power compression of incompatible test cubes
- Patent number 8,832,512
- Issue date Sep 9, 2014
- Mentor Graphics Corporation
- Dariusz Czysz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective per-cycle masking of scan chains for system level test
- Patent number 8,726,113
- Issue date May 13, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test generator for low power built-in self-test
- Patent number 8,683,280
- Issue date Mar 25, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
UNIVERSAL COMPACTOR ARCHITECTURE FOR TESTING CIRCUITS
- Publication number 20220308110
- Publication date Sep 29, 2022
- Siemens Industry Software Inc.
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Application
DETERMINISTIC STELLAR BUILT-IN SELF TEST
- Publication number 20210373077
- Publication date Dec 2, 2021
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Application
Trajectory-Optimized Test Pattern Generation for Built-In Self-Test
- Publication number 20210156918
- Publication date May 27, 2021
- Mentor Graphics Corporation
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Application
FLEXIBLE ISOMETRIC DECOMPRESSOR ARCHITECTURE FOR TEST COMPRESSION
- Publication number 20210018563
- Publication date Jan 21, 2021
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Test Application Time Reduction Using Capture-Per-Cycle Test Points
- Publication number 20180252768
- Publication date Sep 6, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
MULTI-STAGE TEST RESPONSE COMPACTORS
- Publication number 20180156867
- Publication date Jun 7, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELEC...
- Publication number 20180017622
- Publication date Jan 18, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Test Point-Enhanced Hardware Security
- Publication number 20170141930
- Publication date May 18, 2017
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
MULTI-STAGE TEST RESPONSE COMPACTORS
- Publication number 20160320450
- Publication date Nov 3, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
TEST-PER-CLOCK BASED ON DYNAMICALLY-PARTITIONED RECONFIGURABLE SCAN...
- Publication number 20160252573
- Publication date Sep 1, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Deterministic Built-In Self-Test
- Publication number 20160245863
- Publication date Aug 25, 2016
- Mentor Graphics Corporation
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Application
Test Point Insertion For Low Test Pattern Counts
- Publication number 20160109517
- Publication date Apr 21, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELEC...
- Publication number 20160003907
- Publication date Jan 7, 2016
- Mentor Graphics Corporation
- Janusz Rasjki
- G01 - MEASURING TESTING
Information Patent Application
Low Power Testing Based On Dynamic Grouping Of Scan
- Publication number 20150323597
- Publication date Nov 12, 2015
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Test Scheduling and Test Access in Test Compression Environment
- Publication number 20150285854
- Publication date Oct 8, 2015
- Mark A. Kassab
- G01 - MEASURING TESTING
Information Patent Application
Isometric Test Compression With Low Toggling Activity
- Publication number 20150253385
- Publication date Sep 10, 2015
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES
- Publication number 20150160290
- Publication date Jun 11, 2015
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G01 - MEASURING TESTING
Information Patent Application
Fault-Driven Scan Chain Configuration For Test-Per-Clock
- Publication number 20140372820
- Publication date Dec 18, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Scan Chain Stitching For Test-Per-Clock
- Publication number 20140372821
- Publication date Dec 18, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Test Generation For Test-Per-Clock
- Publication number 20140372824
- Publication date Dec 18, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Test-Per-Clock Based On Dynamically-Partitioned Reconfigurable Scan...
- Publication number 20140372818
- Publication date Dec 18, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Scan Chain Configuration For Test-Per-Clock Based On Circuit Topology
- Publication number 20140372819
- Publication date Dec 18, 2014
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST
- Publication number 20140229779
- Publication date Aug 14, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
SCAN-BASED TEST ARCHITECTURE FOR INTERCONNECTS IN STACKED DESIGNS
- Publication number 20140223247
- Publication date Aug 7, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELEC...
- Publication number 20140006888
- Publication date Jan 2, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES
- Publication number 20130305107
- Publication date Nov 14, 2013
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G01 - MEASURING TESTING
Information Patent Application
Test Scheduling With Pattern-Independent Test Access Mechanism
- Publication number 20130290795
- Publication date Oct 31, 2013
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST
- Publication number 20120210181
- Publication date Aug 16, 2012
- Mentor Graphics Corporation
- Janusz Rajski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS
- Publication number 20110320999
- Publication date Dec 29, 2011
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES
- Publication number 20110231722
- Publication date Sep 22, 2011
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G01 - MEASURING TESTING

Jerzy Tyszer

Person

Patents Grantslast 30 patents

Universal compactor architecture for testing circuits

Trajectory-optimized test pattern generation for built-in self-test

Deterministic stellar built-in self test

Flexible isometric decompressor architecture for test compression

Test scheduling and test access in test compression environment

Test application time reduction using capture-per-cycle test points

Test point insertion for low test pattern counts

Scan chain stitching for test-per-clock

Test point-enhanced hardware security

Continuous application and decompression of test patterns and selec...

Low power testing based on dynamic grouping of scan

Multi-stage test response compactors

Deterministic built-in self-test based on compressed test patterns...

Multi-stage test response compactors

Scan-based test architecture for interconnects in stacked designs

Test-per-clock based on dynamically-partitioned reconfigurable scan...

Continuous application and decompression of test patterns and selec...

Isometric test compression with low toggling activity

Selective per-cycle masking of scan chains for system level test

Test generation for test-per-clock

Test-per-clock based on dynamically-partitioned reconfigurable scan...

On-chip comparison and response collection tools and techniques

Continuous application and decompression of test patterns and selec...

Test scheduling with pattern-independent test access mechanism

Scan chain configuration for test-per-clock based on circuit topology

Fault-driven scan chain configuration for test-per-clock

On-chip comparison and response collection tools and techniques

Low power compression of incompatible test cubes

Selective per-cycle masking of scan chains for system level test

Test generator for low power built-in self-test

Patents Applicationslast 30 patents

UNIVERSAL COMPACTOR ARCHITECTURE FOR TESTING CIRCUITS

DETERMINISTIC STELLAR BUILT-IN SELF TEST

Trajectory-Optimized Test Pattern Generation for Built-In Self-Test

FLEXIBLE ISOMETRIC DECOMPRESSOR ARCHITECTURE FOR TEST COMPRESSION

Test Application Time Reduction Using Capture-Per-Cycle Test Points

MULTI-STAGE TEST RESPONSE COMPACTORS

CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELEC...

Test Point-Enhanced Hardware Security

MULTI-STAGE TEST RESPONSE COMPACTORS

TEST-PER-CLOCK BASED ON DYNAMICALLY-PARTITIONED RECONFIGURABLE SCAN...

Deterministic Built-In Self-Test

Test Point Insertion For Low Test Pattern Counts

CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELEC...

Low Power Testing Based On Dynamic Grouping Of Scan

Test Scheduling and Test Access in Test Compression Environment

Isometric Test Compression With Low Toggling Activity

ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES

Fault-Driven Scan Chain Configuration For Test-Per-Clock

Scan Chain Stitching For Test-Per-Clock

Test Generation For Test-Per-Clock

Test-Per-Clock Based On Dynamically-Partitioned Reconfigurable Scan...

Scan Chain Configuration For Test-Per-Clock Based On Circuit Topology

SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

SCAN-BASED TEST ARCHITECTURE FOR INTERCONNECTS IN STACKED DESIGNS

CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELEC...

ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES

Test Scheduling With Pattern-Independent Test Access Mechanism

SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

DECOMPRESSORS FOR LOW POWER DECOMPRESSION OF TEST PATTERNS

ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES