Jesse Ethan Craig

Person

South Burlington, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Functional simulation redundancy reduction by state comparison and...
- Patent number 8,539,404
- Issue date Sep 17, 2013
- International Business Machines Corporation
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip lockout protection scheme for integrated circuit devices and i...
- Patent number 8,484,481
- Issue date Jul 9, 2013
- International Business Machines Corporation
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying non-deterministic behavior of a design under test
- Patent number 8,103,998
- Issue date Jan 24, 2012
- International Business Machines Corporation
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design structure for dynamically selecting compiled instructions
- Patent number 7,865,862
- Issue date Jan 4, 2011
- International Business Machines Corporation
- Deanna J. Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and computer program product for dynamically sele...
- Patent number 7,761,690
- Issue date Jul 20, 2010
- International Business Machines Corporation
- Deanna J. Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-arm disk drive system having interleaved read/write operation...
- Patent number 7,710,683
- Issue date May 4, 2010
- International Business Machines Corporation
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-arm disk drive system having interleaved read/write operation...
- Patent number 7,385,781
- Issue date Jun 10, 2008
- International Business Machines Corporation
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification of the design of an integrated circuit background
- Patent number 7,360,138
- Issue date Apr 15, 2008
- International Business Machines Corporation
- Jesse Ethan Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design verification using checkpointing
- Patent number 7,308,663
- Issue date Dec 11, 2007
- International Business Machines Corporation
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FUNCTIONAL SIMULATION REDUNDANCY REDUCTION BY STATE COMPARISON AND...
- Publication number 20130080983
- Publication date Mar 28, 2013
- International Business Machines Corporation
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Chip Lockout Protection Scheme for Integrated Circuit Devices and I...
- Publication number 20110016326
- Publication date Jan 20, 2011
- International Business Machines Corporation
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL COMPUTING AND DISPLAY SYSTEM AND METHOD
- Publication number 20090251474
- Publication date Oct 8, 2009
- Deanna J. Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERIFYING NON-DETERMINISTIC BEHAVIOR OF A DESIGN UNDER TEST
- Publication number 20090210837
- Publication date Aug 20, 2009
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design Structure for a Clock System for a Plurality of Functional B...
- Publication number 20090172627
- Publication date Jul 2, 2009
- International Business Machines Corporation
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR DYNAMICALLY SELECTING COMPILED INSTRUCTIONS
- Publication number 20090125704
- Publication date May 14, 2009
- International Business Machines Corporation
- Deanna J. Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR DYNAMICALLY SELE...
- Publication number 20090031111
- Publication date Jan 29, 2009
- Deanna J. Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF REDUCING PEAK POWER CONSUMPTION IN AN INTEGRATED CIRCUIT...
- Publication number 20080270965
- Publication date Oct 30, 2008
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-Arm Disk Drive System Having Interleaved Read/Write Operation...
- Publication number 20080225431
- Publication date Sep 18, 2008
- International Business Machines Corporation
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-ARM DISK DRIVE SYSTEM HAVING INTERLEAVED READ/WRITE OPERATION...
- Publication number 20080123213
- Publication date May 29, 2008
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECTED RANDOM VERIFICATION
- Publication number 20070266349
- Publication date Nov 15, 2007
- Jesse Ethan Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERIFICATION OF THE DESIGN OF AN INTEGRATED CIRCUIT BACKGROUND
- Publication number 20070220386
- Publication date Sep 20, 2007
- Jesse Ethan Craig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT DESIGN VERIFICATION USING CHECKPOINTING
- Publication number 20070074135
- Publication date Mar 29, 2007
- International Business Machines Corporation
- Jesse E. Craig
- G06 - COMPUTING CALCULATING COUNTING

Jesse Ethan Craig

Person

Patents Grantslast 30 patents

Functional simulation redundancy reduction by state comparison and...

Chip lockout protection scheme for integrated circuit devices and i...

Verifying non-deterministic behavior of a design under test

Design structure for dynamically selecting compiled instructions

Method, apparatus and computer program product for dynamically sele...

Multi-arm disk drive system having interleaved read/write operation...

Multi-arm disk drive system having interleaved read/write operation...

Verification of the design of an integrated circuit background

Circuit design verification using checkpointing

Patents Applicationslast 30 patents

FUNCTIONAL SIMULATION REDUNDANCY REDUCTION BY STATE COMPARISON AND...

Chip Lockout Protection Scheme for Integrated Circuit Devices and I...

VIRTUAL COMPUTING AND DISPLAY SYSTEM AND METHOD

VERIFYING NON-DETERMINISTIC BEHAVIOR OF A DESIGN UNDER TEST

Design Structure for a Clock System for a Plurality of Functional B...

DESIGN STRUCTURE FOR DYNAMICALLY SELECTING COMPILED INSTRUCTIONS

METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR DYNAMICALLY SELE...

METHOD OF REDUCING PEAK POWER CONSUMPTION IN AN INTEGRATED CIRCUIT...

Multi-Arm Disk Drive System Having Interleaved Read/Write Operation...

MULTI-ARM DISK DRIVE SYSTEM HAVING INTERLEAVED READ/WRITE OPERATION...

DIRECTED RANDOM VERIFICATION

VERIFICATION OF THE DESIGN OF AN INTEGRATED CIRCUIT BACKGROUND

CIRCUIT DESIGN VERIFICATION USING CHECKPOINTING