Jesse H. Jenkins, IV

Person

Danville, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods of implementing output ports and an integrated circuit havi...
- Patent number 8,324,930
- Issue date Dec 4, 2012
- Xilinx, Inc.
- Jesse H. Jenkins, IV
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for and method of minimizing power consumption in an integr...
- Patent number 8,145,923
- Issue date Mar 27, 2012
- Xilinx, Inc.
- Shankar Lakkapragada
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and integrated circuit for secure reconfiguration of program...
- Patent number 8,022,724
- Issue date Sep 20, 2011
- Xilinx, Inc.
- Jesse H. Jenkins, IV
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and arrangement for reducing power in bidirectional input/ou...
- Patent number 7,859,294
- Issue date Dec 28, 2010
- Xilinx, Inc.
- Jesse H. Jenkins, IV
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for counter-based clock signal adaptation
- Patent number 7,786,782
- Issue date Aug 31, 2010
- Xilinx, Inc.
- Scott Te-Sheng Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power estimation for mobile devices
- Patent number 7,574,240
- Issue date Aug 11, 2009
- Xilinx, Inc.
- Jesse H. Jenkins, IV
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for providing secure programmable logic devices
- Patent number 7,536,559
- Issue date May 19, 2009
- Xilinx, Inc.
- Jesse H. Jenkins, IV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power zones for programmable logic devices
- Patent number 7,498,839
- Issue date Mar 3, 2009
- Xilinx, Inc.
- Jesse H. Jenkins, IV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Design security for configurable devices
- Patent number 7,345,502
- Issue date Mar 18, 2008
- Xilinx, Inc.
- Shankar Lakkapragada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable detection of power failure in an integrated circuit
- Patent number 7,345,944
- Issue date Mar 18, 2008
- Xilinx, Inc.
- Jesse H. Jenkins, IV
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods of logic reduction in electrical circuits utilizing fault s...
- Patent number 7,315,802
- Issue date Jan 1, 2008
- Xilinx, Inc.
- Jesse H. Jenkins, IV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and circuits for realizing a performance monitor for a proc...
- Patent number 7,308,564
- Issue date Dec 11, 2007
- Xilinx, Inc.
- Jesse H. Jenkins, IV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface for access to non-volatile memory on an integrated circuit
- Patent number 7,251,168
- Issue date Jul 31, 2007
- Xilinx, Inc.
- Jesse H. Jenkins, IV
- G11 - INFORMATION STORAGE
Information Patent Grant
Segmented configuration of programmable logic devices
- Patent number 7,193,439
- Issue date Mar 20, 2007
- Ilinx, Inc.
- Jesse H. Jenkins, IV
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR COUNTER-BASED CLOCK SIGNAL ADAPTATION
- Publication number 20100079182
- Publication date Apr 1, 2010
- Xilinx, Inc.
- Scott Te-Sheng Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT FOR AND METHOD OF MINIMIZING POWER CONSUMPTION IN AN INTEGR...
- Publication number 20090210731
- Publication date Aug 20, 2009
- Xilinx, Inc.
- Shankar Lakkapragada
- H03 - BASIC ELECTRONIC CIRCUITRY

Jesse H. Jenkins, IV

Person

Patents Grantslast 30 patents

Methods of implementing output ports and an integrated circuit havi...

Circuit for and method of minimizing power consumption in an integr...

Method and integrated circuit for secure reconfiguration of program...

Method and arrangement for reducing power in bidirectional input/ou...

Method and apparatus for counter-based clock signal adaptation

Power estimation for mobile devices

Method and apparatus for providing secure programmable logic devices

Low power zones for programmable logic devices

Design security for configurable devices

Programmable detection of power failure in an integrated circuit

Methods of logic reduction in electrical circuits utilizing fault s...

Methods and circuits for realizing a performance monitor for a proc...

Interface for access to non-volatile memory on an integrated circuit

Segmented configuration of programmable logic devices

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR COUNTER-BASED CLOCK SIGNAL ADAPTATION

CIRCUIT FOR AND METHOD OF MINIMIZING POWER CONSUMPTION IN AN INTEGR...