Jesse H. Jenkins IV

Person

Danville, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Back annotation of output time delays
- Patent number 8,850,377
- Issue date Sep 30, 2014
- Xilinx, Inc.
- Jesse H. Jenkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for automatic self-erasing of programmable log...
- Patent number 8,621,597
- Issue date Dec 31, 2013
- Xilinx, Inc.
- Jesse H. Jenkins
- G11 - INFORMATION STORAGE
Information Patent Grant
Secure reconfiguration of programmable logic
- Patent number 8,593,172
- Issue date Nov 26, 2013
- Xilinx, Inc.
- Jesse H. Jenkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Security improvements for programmable devices
- Patent number 6,788,097
- Issue date Sep 7, 2004
- Xilinx, Inc.
- Jesse H. Jenkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System power control output circuit for programmable logic devices
- Patent number 6,529,041
- Issue date Mar 4, 2003
- Xilinx, Inc.
- Mark M. Ng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for remotely testing microelectronic device over the internet
- Patent number 6,393,591
- Issue date May 21, 2002
- Xilinx, Inc.
- Jesse H. Jenkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with adjustable length delay line
- Patent number 6,316,958
- Issue date Nov 13, 2001
- Xilinx, Inc.
- Jesse H. Jenkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for selecting slew rate for a programmable device
- Patent number 6,184,708
- Issue date Feb 6, 2001
- Xilinx, Inc.
- Jesse H. Jenkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of minimizing power use in programmable logic devices
- Patent number 6,172,518
- Issue date Jan 9, 2001
- Xilinx, Inc.
- Jesse H. Jenkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bus-hold circuit having a defined state during set-up of an in-syst...
- Patent number 6,172,519
- Issue date Jan 9, 2001
- Xilinx, Inc.
- David Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
One-cold encoding method for low power operation in a complex progr...
- Patent number 6,167,560
- Issue date Dec 26, 2000
- Xilinx, Inc.
- Jesse H. Jenkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Slew rate selection circuit for a programmable device
- Patent number 6,020,757
- Issue date Feb 1, 2000
- Xilinx, Inc.
- Jesse H. Jenkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable voltage stabilizing circuit for a programmable integra...
- Patent number 5,742,178
- Issue date Apr 21, 1998
- Xilinx, Inc.
- Jesse H. Jenkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed product term allocation structure supporting logic itera...
- Patent number 5,563,529
- Issue date Oct 8, 1996
- Xilinx, Inc.
- Jeffrey H. Seltzer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cross point interconnect structure with reduced area
- Patent number 5,530,378
- Issue date Jun 25, 1996
- Xilinx, Inc.
- Nicholas Kucharewski
- H03 - BASIC ELECTRONIC CIRCUITRY

Jesse H. Jenkins IV

Person

Patents Grantslast 30 patents

Back annotation of output time delays

Apparatus and method for automatic self-erasing of programmable log...

Secure reconfiguration of programmable logic

Security improvements for programmable devices

System power control output circuit for programmable logic devices

Method for remotely testing microelectronic device over the internet

Programmable logic device with adjustable length delay line

Method for selecting slew rate for a programmable device

Method of minimizing power use in programmable logic devices

Bus-hold circuit having a defined state during set-up of an in-syst...

One-cold encoding method for low power operation in a complex progr...

Slew rate selection circuit for a programmable device

Programmable voltage stabilizing circuit for a programmable integra...

High speed product term allocation structure supporting logic itera...

Cross point interconnect structure with reduced area