Jian Mao

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Merged data path for triangle and box intersection test in ray tracing
- Patent number 11,276,223
- Issue date Mar 15, 2022
- Advanced Micro Devices, Inc.
- Skyler Jonathon Saleh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid active noise control system
- Patent number 11,189,261
- Issue date Nov 30, 2021
- Shenzhen Goodix Technology Co., Ltd.
- Youhong Lu
- G10 - MUSICAL INSTRUMENTS ACOUSTICS
Information Patent Grant
Matrix multiplier with submatrix sequencing
- Patent number 11,093,580
- Issue date Aug 17, 2021
- Advanced Micro Devices, Inc.
- Maxim V. Kazakov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computation reduced tessellation
- Patent number 9,142,060
- Issue date Sep 22, 2015
- QUALCOMM Incorporated
- Nariman Moezzi Madani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage structures for stitching primitives in graphics processing
- Patent number 9,082,204
- Issue date Jul 14, 2015
- QUALCOMM Incorporated
- Vineet Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual channel memory architecture having reduced interface pin requi...
- Patent number 8,325,525
- Issue date Dec 4, 2012
- QUALCOMM Incorporated
- Jian Mao
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Hybrid single and dual channel DDR interface scheme by interleaving...
- Patent number 8,098,539
- Issue date Jan 17, 2012
- QUALCOMM Incorporated
- Raghu Sankuratri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual channel memory architecture having a reduced interface pin req...
- Patent number 7,804,735
- Issue date Sep 28, 2010
- QUALCOMM Incorporated
- Jian Mao
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Patents Applicationslast 30 patents

Information Patent Application
HYBRID ACTIVE NOISE CONTROL SYSTEM
- Publication number 20210375255
- Publication date Dec 2, 2021
- Shenzhen Goodix Technology Co., Ltd.
- Youhong Lu
- G10 - MUSICAL INSTRUMENTS ACOUSTICS
Information Patent Application
MERGED DATA PATH FOR TRIANGLE AND BOX INTERSECTION TEST IN RAY TRACING
- Publication number 20200193682
- Publication date Jun 18, 2020
- ADVANCED MICRO DEVICES, INC.
- Skyler Jonathon Saleh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MATRIX MULTIPLIER WITH SUBMATRIX SEQUENCING
- Publication number 20200133991
- Publication date Apr 30, 2020
- ADVANCED MICRO DEVICES, INC.
- Maxim V. KAZAKOV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORAGE STRUCTURES FOR STITCHING PRIMITIVES IN GRAPHICS PROCESSING
- Publication number 20140063014
- Publication date Mar 6, 2014
- QUALCOMM Incorporated
- Vineet Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTATION REDUCED TESSELLATION
- Publication number 20140063012
- Publication date Mar 6, 2014
- QUALCOMM Incorporated
- Nariman Moezzi Madani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hybrid Single and Dual Channel DDR Interface Scheme by Interleaving...
- Publication number 20110055617
- Publication date Mar 3, 2011
- QUALCOMM Incorporated
- Raghu Sankuratri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dual Channel Memory Architecture Having Reduced Interface Pin Requi...
- Publication number 20100318730
- Publication date Dec 16, 2010
- QUALCOMM Incorporated
- Jian Mao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dual Channel Memory Architecture Having a Reduced Interface Pin Req...
- Publication number 20090219779
- Publication date Sep 3, 2009
- QUALCOMM Incorporated
- Jian Mao
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Merged data path for triangle and box intersection test in ray tracing

Hybrid active noise control system

Matrix multiplier with submatrix sequencing

Computation reduced tessellation

Storage structures for stitching primitives in graphics processing

Dual channel memory architecture having reduced interface pin requi...

Hybrid single and dual channel DDR interface scheme by interleaving...

Dual channel memory architecture having a reduced interface pin req...

Patents Applicationslast 30 patents

HYBRID ACTIVE NOISE CONTROL SYSTEM

MERGED DATA PATH FOR TRIANGLE AND BOX INTERSECTION TEST IN RAY TRACING

MATRIX MULTIPLIER WITH SUBMATRIX SEQUENCING

STORAGE STRUCTURES FOR STITCHING PRIMITIVES IN GRAPHICS PROCESSING

COMPUTATION REDUCED TESSELLATION

Hybrid Single and Dual Channel DDR Interface Scheme by Interleaving...

Dual Channel Memory Architecture Having Reduced Interface Pin Requi...

Dual Channel Memory Architecture Having a Reduced Interface Pin Req...